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Compare 769 IP from 57 vendors (1 - 10)
  • MIPI C/D Combo TX PHY and DSI controller
    • High Data Rates: Supports data transmission rates
    • Energy Efficiency: Optimized for low power consumption, making it ideal for battery-powered devices
    • Complete Solution: Combines the MIPI CD-PHY Transmitter PHY and DSI Controller to make it a one-stop solution
    • Flexible IP Configuration




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  • MIPI D-PHY TX PHY and DSI controller
    • Scalability and Flexibility: Supports multiple data lanes for higher aggregate bandwidth, any of the multiple lanes can be configured into Clock Lane
    • High Data Rates: Supports data transmission rates up to 4.5Gbps per lane, allowing for high-resolution displays and smooth refresh rates
    • Energy Efficiency: Optimized for low power consumption, making it ideal for battery-powered devices
    • Complete Solution: Combines the MIPI D-PHY Transmitter PHY and DSI Controller to make it a one-stop solution
    Block Diagram -- MIPI D-PHY TX PHY and DSI controller
  • MIPI SoundWire Slave Controller 1.2
    • MIPI SoundWire®Slave Controller, typically integrated into audio DSP/Codecs or directly into audio peripherals such as Microphones and Amplifiers used in smart phones, tablets and mobile PCs. 
    • The IP when integrated provides SoundWire, a new audio interface to connect to Master typically embedded in Application Processor or Audio Codecs.
    Block Diagram -- MIPI SoundWire Slave Controller 1.2
  • MIPI SoundWire Master Controller 1.2
    • Compliant with MIPI SoundWire specification version 1.2
    • Configurable number of Data Ports Configurable Direction – Source or Sink
    • Implements clock gearbox with programmable frequency divider
    • Implements SoundWire Bus Clock Stop and WakeUp detection
    Block Diagram -- MIPI SoundWire Master Controller 1.2
  • MIPI SLIMbus Software Stack
    • Compliant with MIPI SLIMbus® Specification version 1.01
    • Portability in choice of OS, processors and hardware
    • Easy-to-use interface for applications
    • Fully documented generic interface API
    Block Diagram -- MIPI SLIMbus Software Stack
  • MIPI M-PHY® 3.1 Analog Transceiver
    • The M-PHYs are of Type 1, which apply to UFS, LLI and CSI-3 protocols.
    • The Multi-gear M-PHY 3.0 consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII.
    • The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
    Block Diagram -- MIPI M-PHY® 3.1 Analog Transceiver
  • MIPI D-PHY v2.1 IP Core
    • Compliant to MIPI® Alliance Standard for D-PHY specification Version 2.1
    • Supports D-PHY 1.1 synchronous transfer mode at high speed mode with a bit rate of 80-1500 Mb/s without deskew calibration
    • Supports DPHY 1.2 for 1500 – 2500 Mb/s with deskew calibration.
    Block Diagram -- MIPI D-PHY v2.1 IP Core
  • MIPI D-PHY Analog Transceiver IP Core
    • The MIPI D-PHY Analog Transceiver IP Core is fully compliant with the D-PHY specification version 1.1.
    • It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols at speeds up to 1.5Gbps per lane.
    • It is a Universal PHY that can be configured as a transmitter, receiver, or transceiver.
    Block Diagram -- MIPI D-PHY Analog Transceiver IP Core
  • Combination MIPI CPHY-DPHY Analog Interface
    • The MIPI C-PHY V1.2 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock.
    • It is intended to be used for camera interface (CSI-2 v1.3) and display interface (DSI-2 v1.0).
    • The signaling interface uses a 3-phase transceiver that encodes 3-bit symbols over 3 wires
    Block Diagram -- Combination MIPI CPHY-DPHY Analog Interface
  • MIPI CPHY v1.1 Analog Interface
    • The MIPI CPHY V1.1 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock.
    • It is intended to be used for camera interface (CSI-2 v1.3) and display interface (DSI-2 v1.0).
    • The signaling interface uses a 3-phase transceiver that encodes 3-bit symbols over 3 wires. This is different from the two-wire differential “lane” used in D-PHY.
    Block Diagram -- MIPI CPHY v1.1 Analog Interface
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