Low Leakage SRAM Compiler IP
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GLOBALFOUNDRIES 22nm Low Leakage Single-Port SRAM Compiler
- Low Leakage
- Low Power
- High Density
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Single Port SRAM compiler - Memory optimized for ultra low leakage and high density - Dual Voltage - compiler range up to 640 k
- Available for Free Download and Use
- Source biasing implementation for ultra low leakage
- 4 times less leakage compared to stand by mode
- 3 times less leakage compared to retention mode
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Single port SRAM Compiler - low power retention mode
- Uses low leakage devices and source biasing to minimize standby currents.
- Dedicated standy mode with built in source biasing for the memory array.
- Periphery and array supplies are isolated to allow power off of the perphery when in standy mode.
- .8V supply voltage
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Bulk 40ULP single port SRAM Compiler - ultra low power, low power retention mode
- Uses low leakage devices and source biasing to minimize standby currents.
- Dedicated standy mode with built in source biasing for the memory array.
- Periphery and array supplies are isolated to allow power off of the perphery when in standy mode.
- .8V supply voltage
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Low Power Memory Compiler - Single Port SRAM - GF 22nm FDX
- Silicon proven Single Port SRAM compiler for GF22 FDX - Memory optimized for low power and supports body biasing.
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Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
- Reduced die cost
- Pushed rule bit cell from foundry
- Ultra low power
- Low voltage operation down to 1.2 V
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Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
- Reduced die cost
- Pushed rule bit cell from foundry
- Ultra low power
- Low voltage operation down to 1.2 V
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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery