Low Leakage SRAM Compiler IP
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GLOBALFOUNDRIES 22nm Low Leakage Single-Port SRAM Compiler
- Low Leakage
- Low Power
- High Density
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Single Port SRAM compiler - Memory optimized for ultra low leakage and high density - Dual Voltage - compiler range up to 640 k
- Available for Free Download and Use
- Source biasing implementation for ultra low leakage
- 4 times less leakage compared to stand by mode
- 3 times less leakage compared to retention mode
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Single Port SRAM with low power retention mode, high speed pins on 1 side
- Ultra low power data retention. Memory instances generated by the Bulk 22ULL go into a deep sleep mode that retains data at minimal power consumption.
- Self biasing. The SP SRAM 22ULL internal self-biasing capabilities provide ease of IP integration.
- High yield. To ensure high manufacturing yield, bulk 22ULL uses low leakage 6T (0.110µ2) bit cells and is consistent with Design for Manufacturing (DFM) guidelines for the Bulk 22ULL process.
- High usability. All signal and power pins are available on metal 4 while maintaining routing porosity in metal 4. Power pins can optionally be made available on metal 5 to simplify the power connections at the chip level.
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SMIC 0.18umLL Single-Port/Dual-Port SRAM, Two-Port Register File and Diffusion ROM Compiler
- Low Power
- Low Leakage
- High Density
- High Speed
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- ConfigurationSVT/HVT MOS for memory peripheryuHD HVT pushed rule bit-cell from foundry Designed with 4 metal layers, routing enabled over the memory in metal 4 within free routing tracksMigration on an existing architecture already available for other processes (90, 85, 55 nm)Smart periphery design to reach the highest densityUp to 20% denser than standard memory generators at 55 nmUltra low leakage designData retention mode at nominal voltage (1.2 V) and low voltage (0.7 V): for 4x leakage reductionLow dynamic powerPartitioned arrayVariable write-mask capability Easy integrationMUX optionsData range flexibility allows easy addition of bits for redundancy or ECC purposesAddress range flexibility allows easy addition of single rows for redundancy purposes The Dolphin qualityComplete mismatch validation of the memory architecture taking in account local and global dispersionOptional BIST for industrial fabrication test of instances
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Bulk 40ULP Single Port SRAM with low power retention mode, high speed pins on 1 side
- Ultra low power data retention. Memory instances generated by the Bulk 40 ULPgo into a deep sleep mode that retains data at minimal power consumption.