Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
Overview
Single Port SRAM compiler - TSMC 180 nm uLL - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
Key Features
- Reduced die cost
- Pushed rule bit cell from foundry
- Ultra low power
- Low voltage operation down to 1.2 V
- Multi-plane architecture
- Optional Byte write mode
- A Dual Voltage variant of this product is also available
- Ultra low leakage
- Stand by mode
- Data retention mode
- 260 times less leaky in retention mode compared with the PLUTON eLC-RR option in G process!
- This translates into 500 times less leakage compared to simple stand-by mode
- Easy integration
- Mux factor can be chosen
- Deliverables compatible with Top Metal 4 or Top Metal 5 or +
- Wide flexibility for words and bits per word
- The Dolphin quality
- Silicon Proven architecture
- Design methodology ensuring functionality at low voltage
Technical Specifications
Maturity
In_Production
TSMC
In Production:
180nm
ULL
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- Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k