LPDDR2 IP
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262
IP
from 11 vendors
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10)
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LPDDR2 IP solution
- Compatible with LPDDR2 up to 1066Mbps
- AXI compliant multi-ports, and data width, FIFO depth, command queue depth configurable
- DFI compliant interface between controller and PHY
- Support ECC (error correcting code)
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LPDDR2 Synthesizable Transactor
- Supports 100% of LPDDR2 protocol standard JESD209-2E and JESD209-2F
- Supports all the LPDDR2 commands as per the specs
- Supports up to 32GB device density
- Supports following devices:
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LPDDR2 Memory Model
- Supports LPDDR2 memory devices from all leading vendors.
- Supports 100% of LPDDR2 protocol standard JESD209-2E and JESD209-2F.
- Supports all the LPDDR2 commands as per the specs.
- Supports up to 32GB device density
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LPDDR2 DFI Verification IP
- Compliant with DFI version 2.1 or higher Specifications.
- Supports LPDDR2 devices compliant with JEDEC LPDDR2 SDRAM Standard JESD209-2F.pdf and JESD209-2E.pdf
- Supports for Read data-eye training
- Supports for Read gate training
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LPDDR2 Controller IIP
- Supports LPDDR2 protocol standard JESD209-2E and JESD209-2F Specification
- Compliant with DFI version 2.1 or higher Specification.
- Supports up to 16 AXI ports with data width upto 512 bits.
- Supports controllable outstanding transactions for AXI write and read channels
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LPDDR2 Assertion IP
- Specification Compliance
- Supports LPDDR2 memory devices from all leading vendors.
- Supports 100% of LPDDR2 protocol standard JESD209-2E and JESD209-2F.
- Supports all the LPDDR2 commands as per the specs.
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LPDDR2 DFI Assertion IP
- Specification Compliance
- Compliant with DFI version 2.1 or higher Specifications.
- Supports LPDDR2 devices compliant with JEDEC LPDDR2 SDRAM Standard JESD209-2F.pdf and JESD209-2E.pdf.
- Supports for Read data-eye training.
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Performance Enhanced version of uMCTL2 supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3 and LPDDR2 for Automotive
- Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
- Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
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Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
- Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
- Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
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DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
- Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
- Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces