IP Catalog > JESD204B SERDES

JESD204B SERDES IP

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Compare 9 IP from 4 vendors (1 - 9)
  • JESD204B Transmitter IIP
    • Compliant with JESD204 specification JESD204A, JESD204B.01.
    • Full JESD204B transmit functionality.
    • Supports data rate upto 12.5 Gbps.
    • Supports programmable clock frequency up to 12.5 GHz.
    Block Diagram -- JESD204B Transmitter IIP
  • JESD204B Receiver IIP
    • Compliant with JESD204 specification JESD204A, JESD204B.01.
    • Full JESD204B receive functionality.
    • Supports data rate upto 12.5 Gbps.
    • Supports programmable clock frequency up to 12.5 GHz.
    Block Diagram -- JESD204B Receiver IIP
  • 16G Multiproocol Serdes IP, Silicon Proven in TSMC 28HPC+
    • Multiple lanes transceiver with data rate from 1Gbps to 16Gbps
    • Transceiver version including both receiver and transmitter
    • Transmitter only version
    • 40bit/32bit/20bit/16bit selectable parallel data bus
  • MIPHY Consumer SerDes IP, Silicon Proven in ST 28FDSOI
    • Consumer Application SERDES
    • From 1.125Gb/s to 8Gb/s/ 10Gbs
    • Technology: 28FDSOI 8ML & 10ML
    • Support multi lane configuration
    Block Diagram -- MIPHY Consumer SerDes IP, Silicon Proven in ST 28FDSOI
  • Multi Standard programmable SERDES PHY with single/multi-lane configurations with support of long-reach channel
    • Single SERDES Design that meets wide range of Standards, Protocols and Speeds.
    • Any combination is possible, e.g. USB-3.0, PCIe Gen-3 and SATA Gen-3 in a single Combo SERDES.
    • Internal Low Jitter PLL support the various standards clocking requirements- no need for additional components.
    • Flexible Design- Tile Based Design that enable customer to select any number of Tx and Rx Lanes.
  • JESD204B Controller IP
    • Designed to JEDEC JESD204B.01 specification
    • Line rates from 1 Gbps to 12.5 Gbps (with optional extension to 16 Gbps)
    • Supports 1-24 lanes
    • Supports 1-96 converters
    Block Diagram -- JESD204B Controller IP
  • JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
    • Widest feature set available in market.
    • Scrambling and de-scrambling Included.
    • High performance transport layer support.
    • Build in test functions
    Block Diagram -- JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
  • JESD204C Controller IP
    • Designed to JEDEC JESD204C.1 specification
    • Line rates from 1 Gbps to 32.5 Gbps
    • Supports 1-24 lanes
    • Supports 1-96 converters
    Block Diagram -- JESD204C Controller IP
  • JESD204 Verification IP
    • This JESD204 Verification IP provides an advanced and efficient solution for verifying and debugging these standards in a UVM simulation environment.
    • The verification IP helps reduce time to test, accelerate verification process and ensures a high quality for the end-product.
    Block Diagram -- JESD204 Verification IP
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