Industry Leading, Silicon Proven, 32.5 Gbps per lane IP core, backed by a complete portfolio of verification tools, PHY interop, and hardware demos
The JESD204C controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C.1 serial interface standard targeting both ASICs and FPGAs. The IP core supports line speeds up to 32.5 Gbps per lane with 64b 66b encoding and includes full backwards compatibility with JESD204B and its 8b 10b encoding. The IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements.
The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.
JESD204C delivers all the features of the standard. The solution includes separate RX,TX modules containing the link layer and transport layer. The IP is backward compatible with JESD204B
Gearboxes are included to enable easy interfacing to any SERDES width. The IP is interoperability tested with leading PHY and data convertor vendors.
JESD204C delivers all the features of the standard. The solution includes separate RX,TX modules containing the link layer and transport layer. The IP is backward compatible with JESD204B
Gearboxes are included to enable easy interfacing to any SERDES width. The IP is interoperability tested with leading PHY and data convertor vendors.
