The JESD204C controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C.1 serial interface standard targeting both ASICs and FPGAs. The IP core supports line speeds up to 32.5 Gbps per lane with 64b 66b encoding and includes full backwards compatibility with JESD204B and its 8b 10b encoding. The IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements.
The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.
JESD204C
Overview
Key Features
- Delivering Performance
- Designed to JEDEC JESD204C.1 specification
- Line rates from 1 Gbps to 32.5 Gbps
- Supports 1-24 lanes
- Supports 1-96 converters
- HD-mode supported
- Performs user-enabled scrambling
- Generates initial lane alignment sequence
- Performs the alignment character generation
- Checks link configuration data with user selected parameter values during initial lane synchronization sequence
- 8b 10b, 64b 66b, 64b 80b encoding/decoding supported
- Verilog-based
- Optional data mapping and de-mapping
- Supports Subclasses (0, 1, and 2) on the 64b 66b link layer
- Interoperability
- JESD204C IP has been interoperability tested with Analog Devices JESD204C implementation
- Easy to use
- HW demonstration platform available
- VIP and regression test suite available
- SerDes interoperability with several major vendors
- Simple test bench is included
- Silicon Agnostic
- Designed in Verilog and targeting both ASICs and FPGAs
Benefits
- Highly tested solution with extremely wide parameter set enabled
- Has the ability to limit the maximum size of the core to fit with the exact implementation required
- Includes new features like 64b66b, FEC, CMD and CRC.
- Delivering 32.5 Gbps lane speeds on up to 24 lanes
- Silicon Agnostic. Can be tested on FPGA and taken to ASIC
- Interoperability tested
Block Diagram
Applications
- Wireless Base Stations
- Radio systems
- Radar
- UItrasound
- Medical Imaging
- Military communication
- General data communication with JESD204C enabled ADC’s or DAC’s
Deliverables
- The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide
- Simulation Environment, including Simple Testbed, Test case, Test Script
- Timing Constraints in Synopsys SDC format
- Access to support system and direct support from Comcores Engineers
- Test Report
- Synopsys SGDC Files
- Synopsys Lint, CDC and Waivers
Technical Specifications
Maturity
Mature
Availability
Available