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JESD204B PHY IP

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Search (87)
Compare 87 IP from 9 vendors (1 - 10)
  • JESD204B PHY
    • 1.25Gbps to 11.2Gbps continues per-lane data rate range
    • 2 lanes, 4 lanes, 8 lanes to support
    • Tolerate max +/-6000ppm input frequency offset
    • Support 204B deterministic latency
  • JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
    • Widest feature set available in market.
    • Scrambling and de-scrambling Included.
    • High performance transport layer support.
    • Build in test functions
    Block Diagram -- JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
  • JESD204B Tx-Rx PHY IP, Silicon Proven in SMIC 40LL
    • Multiple lanes transceiver with data rate from 1Gbps to 16Gbps: Transceiver version including both receiver and transmitter Transmitter only version available
    • 40bit/32bit/20bit/16bit selectable parallel data bus Independent per-lane power down control
    • Programmable transmit amplitude
    • Programmable 3-tap feed forward equalizer (FFE)
  • JESD204B Tx-Rx PHY IP, Silicon Proven in SMIC 28SF
    • Multiple lanes transceiver with data rate from 1Gbps to 16Gbps: Transceiver version including both receiver and transmitter
    • Transmitter only version available
    • 40bit/32bit/20bit/16bit selectable parallel data bus Independent per-lane power down control
    • Programmable transmit amplitude
  • JESD204B Tx-Rx PHY IP, Silicon Proven in UMC 55SP
    • Multiple lanes transceiver with data rate from 1Gbps to 16Gbps: Transceiver version including both receiver and transmitter
    • Transmitter only version available
    • 40bit/32bit/20bit/16bit selectable parallel data bus Independent per-lane power down control
    • Programmable transmit amplitude
  • JESD204B Tx-Rx PHY IP, Silicon Proven in UMC 28HPC
    • Multiple lanes transceiver with data rate from 1Gbps to 16Gbps: Transceiver version including both receiver and transmitter
    • Transmitter only version available
    • 40bit/32bit/20bit/16bit selectable parallel data bus Independent per-lane power down control
    • Programmable transmit amplitude
  • JESD204B Tx-Rx PHY IP, Silicon Proven in SMIC 14SF++
    • Multiple lanes transceiver with data rate from 1Gbps to 16Gbps: Transceiver version including both receiver and transmitter
    • Transmitter only version available
    • 40bit/32bit/20bit/16bit selectable parallel data bus Independent per-lane power down control
    • Programmable transmit amplitude
  • JESD204B Tx-Rx PHY IP, Silicon Proven in SMIC 12SF++
    • Multiple lanes transceiver with data rate from 1Gbps to 16Gbps: Transceiver version including both receiver and transmitter
    • Transmitter only version available
    • 40bit/32bit/20bit/16bit selectable parallel data bus Independent per-lane power down control
    • Programmable transmit amplitude
  • JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 55LP
    • Multiple lanes transceiver with data rate from 1Gbps to 16Gbps: Transceiver version including both receiver and transmitter
    • Transmitter only version available
    • 40bit/32bit/20bit/16bit selectable parallel data bus Independent per-lane power down control
    • Programmable transmit amplitude
  • JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 28HPC+
    • Multiple lanes transceiver with data rate from 1Gbps to 16Gbps: Transceiver version including both receiver and transmitter
    • Transmitter only version available
    • 40bit/32bit/20bit/16bit selectable parallel data bus Independent per-lane power down control
    • Programmable transmit amplitude
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