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Compare 57 IP from 14 vendors (1 - 10)
  • IPsec ESP IP core for FPGA
    • Built on the success of Helion's industry proven cryptographic IP cores, the Helion ESP Engine provides hardware acceleration of the key cryptographic algorithms and packet processing required by the IPsec Encapsulating Security Payload (ESP) protocol.
    • Its modular architecture provides the flexibility to support only those cryptographic algorithms required for a particular application to provide the optimum logic area and performance trade-off.
    Block Diagram -- IPsec ESP IP core for FPGA
  • IPSec Verification IP
    • Provides Ethernet fully compliant to 802.3-2018 supporting all media independent interfaces for (1/10/25/40/50/100/200/400/800 G)
    • Provides IPSec as per RFC-4301 specification
      • Supports Tunnel Mode and Transport Mode
      • Supports Authentication header (AH)
      • Supports Encapsulating Security Payload (ESP)
      • Supports Manual as well as automatic Key Exchange
      • Encodes and decodes Ip headers
      • Protects and validates ipSec using AES-GCM Cipher suites
      • Cryptographic protection
    • Supports Tunnel Mode and Transport Mode
    • Supports Authentication header (AH)
    Block Diagram -- IPSec Verification IP
  • IPsec - Extreme-Speed Variant
    • Moderate resource requirements
    • High throughput up to 100s of Gbps
    • Compliant with RFC 4303
    • Powered by AES256-GCM
    Block Diagram -- IPsec - Extreme-Speed Variant
  • Quantum Safe IPsec Toolkit
    • Quantum Safe IPsec Toolkit (QuickSec Quantum) is first to market, complete IPsec software implementation with Quantum Safe cryptography support.
    • Quantum Safe cryptography is designed to be resistant to quantum computer attacks and is required by any up-to-date security product.
  • IPsec Engine
    • Can aggregate several 10, 40 or 100 GBE link
    • Throughput from 10 Gbps up to 100 Gbps
    Block Diagram -- IPsec Engine
  • IPsec Security Processor
    • Support for IPv4 and IPv6 packets
    • Support for the IPsec ESP and AH protocols:
    • Support for IPsec ESP encryption algorithms per RFC 4835:
    • Support for IPsec ESP (and AH for –AH option) authentication algorithms per RFC 4835:
  • Standalone stateful hash-based signatures software library
    • The SHSlib is a standalone stateful hash-based signatures software library, which provides signature verification for stateful hash-based signatures.
    • SHSlib implements SHA-256 operation in software and has hardware integration with the EIP-120. In addition, it can be integrated with another hardware SHA core for acceleration.
  • Ethernet Switch/Router IPSec/MACSec 9x10G + 2x40G
    • 9 ports of 10 Gigabit Ethernet.
    •  2 ports of 40 Gigabit Ethernet.
    •  Full wire-speed on all ports and all Ethernet frame sizes.
    •  Store and forward shared memory architecture.
    •  Support for jumbo packets up to 32733 bytes.
    Block Diagram -- Ethernet Switch/Router IPSec/MACSec 9x10G + 2x40G
  • 1.6T/3.2T Multi-Channel MACsec Engine with TDM Interface (MACsec-IP-364)
    • The MACsec-IP-364 is a MACsec/IPsec engine developed specifically for high-speed, multi-rate and multi-port Ethernet devices.
    • Its architecture provides an optimal multi-protocol solution for aggregate throughput for 1.6T and 3.2T.
    • The MACsec-IP-364 is ideal for deployment in data center, enterprise and carrier network applications, as well as network-attached high-performance computing.
    Block Diagram -- 1.6T/3.2T Multi-Channel MACsec Engine with TDM Interface (MACsec-IP-364)
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