I3C Host IP

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Compare 19 IP from 7 vendors (1 - 10)
  • I3C Host Controller
    • Compliant with MIPI I3C Specification V1.0
    • Supports up to 12.5 MHz operation using Push-Pull.
    Block Diagram -- I3C Host Controller
  • MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification
    • Conforms to MIPI I3C v1.1 specifications
    • MIPI Manufacturer ID: 0x03B3
    • Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
    • Legacy I2C messaging
  • MIPI I3C PHY - TSMC (12nm, 7nm, 5nm, and 22nm) - GF 12nm
    • Two wire serial interface up to 12.5 MHz using Push-Pull
    • Legacy I2C Device co-existence on the same Bus (with some limitations)
    • Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
    • Legacy I2C messaging
    Block Diagram -- MIPI I3C PHY - TSMC (12nm, 7nm, 5nm, and 22nm) - GF 12nm
  • MIPI I3C Basic Secondary Controller
    • I3C Basic Secondary Controller
    • Up to 12.5 Mbit/s, SDR-Capable and HDR-Tolerant
    • Autonomous processing of Broadcast and Direct Common Command Codes (CCCs) relevant to an I3C Basic target
    • Hot-Join Mechanism
    Block Diagram -- MIPI I3C Basic Secondary Controller
  • MIPI I3C Basic Target
    • I3C-Basic, up to 12.5 Mbit/s SDR-Capable and HDR-Tolerant Target
    • Autonomous processing of all Broadcast and Direct Common Command Codes (CCCs) relevant to an I3C-Basic target.
    • Hot-Join Mechanism
    • In-Band Interrupts I3C Bus and Device Characteristic Registers (BCR & DCR),
    Block Diagram -- MIPI I3C Basic Target
  • MIPI I3C Slave To AXI Bridge IP
    • Compliant with the I3C version 2.0 specification.
    • Full MIPI I3C Slave functionality.
    • Convert MIPI I3C Transactions into AXI write or read instructions
    • Allows external devices to access the internal AXI Bus
  • MIPI I3C Slave To AHB Bridge IP
    • Compliant with MIPI I3C version 2.0 specification.
    • Full MIPI I3C Slave functionality.
    • Converts MIPI I3C Transactions into AHB write or read instructions
    • Allows external devices to access the internal AHB Bus
  • MIPI I3C Slave IP
    • Compliant with MIPI I3C version 1.1 specification.
    • Full MIPI I3C Slave functionality.
    • Two wire serial interface up to 12.5 MHz using Push-Pull with the following Data rates supported.
    • Supports the following topologies
  • MIPI I3C Master IP
    • Compliant with MIPI I3C version 1.1 and I3C HCI version 1.1 specifications.
    • Non HCI Version is also supported for designs which are gate count sensitive.
    • Full MIPI I3C Master Functionality.
    • Two wire serial interface up to 12.5 MHz using Push-Pull with the following Data rates supported:
  • SPD5118 Hub Controller IP
    • Time saving and Easy to integrated in your SoC
    • Compliance as per JEDEC specification
    Block Diagram -- SPD5118 Hub Controller IP
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