IP Catalog > Half-Power SERDES

Half-Power SERDES IP

Filter
Filter
Search (6)
Compare 6 IP from 1 vendors (1 - 6)
  • UHS2 Host Phy
    • SD Specifications Part 1 UHS-II Specification Volume 2: PHY Draft Version 0.9
    • SD Specifications Part 1 UHS-II Specification Volume 1: System and Protocol Draft Version 0.91
    • (Will be SD4.0 Version1.0 compliance when the standard is released)
    • Bi-directional receiver/transmitter (2ch) supporting both Full Duplex and Half Duplex modes
    Block Diagram -- UHS2 Host Phy
  • UHS2 Device Phy
    • SD Specifications Part 1 UHS-II Specification Volume 2: PHY Draft Version 0.9
    • SD Specifications Part 1 UHS-II Specification Volume 1: System and Protocol Draft Version 0.91
    • (Will be SD4.0 Version1.0 compliance when the standard is released)
    • Bi-directional receiver/transmitter (2ch) supporting both Full Duplex and Half Duplex modes
    Block Diagram -- UHS2 Device Phy
  • SD4.1 UHS- II PHY IP
    • SD 4.1 compliant SDHC/SDXC UHS-II Physical Layer for Host
    • 16bit interface to Link layer
    • Supports both Full Duplex mode and Half Duplex mode
    Block Diagram -- SD4.1 UHS- II PHY IP
  • USB 3.1 Type-C PHY IP, Silicon Proven in TSMC 55ULP
    • Support half rate mode (5Gbps) and full rate mode (10Gbps)
    • Tolerate max +/-7000ppm input frequency offset
    • 32bit/40bit selectable parallel data bus
    • Programmable transmit amplitude
    Block Diagram -- USB 3.1 Type-C PHY IP, Silicon Proven in TSMC 55ULP
  • USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 12SF++
    • Support half rate mode (5Gbps) and full rate mode (10Gbps)
    • Tolerate max +/-7000ppm input frequency offset
    • 32bit/40bit selectable parallel data bus
    • Programmable transmit amplitude
    Block Diagram -- USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 12SF++
  • USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
    • Support half rate mode (5Gbps) and full rate mode (10Gbps)
    • Tolerate max +/-7000ppm input frequency offset
    • 32bit/40bit selectable parallel data bus
    • Programmable transmit amplitude
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
×
Semiconductor IP