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HBM PHY IP

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Search (55)
Compare 55 IP from 17 vendors (1 - 10)
  • TSMC CLN5FF HBM PHY IP
    • High Bandwidth Memory (HBM) DRAM PHY
    • Supports HBM 3.6Gbps
    • Supports DFI 1:2
    • Supports only BL4
  • TSMC CLN16FFGL+ HBM PHY IP
    • High Bandwidth Memory (HBM) DRAM PHY
    • Supports HBM 2Gbps
    • Supports DFI 1:2
    • Supports only BL4
  • Verification IP for HBM
    • HBM VIP is a comprehensive memory VIP solution portfolio for high bandwidth memory (HBM), targeting a new standard in memory performance, density, power consumption, and cost.
    • HBM VIP is intended for SoC and memory control ler designers who employ external HBM modules and PHY developers to ensure both comprehensive verification and protocol and timing compliance.
    Block Diagram -- Verification IP for HBM
  • HBM DFI Synthesizable Transactor
    • Compliant with DFI version 4.0 or 5.0 Specifications.
    • Supports HBM devices compliant with JEDEC HBM DRAM Standard JESD235, JESD235A, JESD235B and JESD235C.
    • Supports all Interface Groups.
    • Supports Write Transactions with Data mask
    Block Diagram -- HBM DFI Synthesizable Transactor
  • HBM DFI Verification IP
    • Compliant with DFI version 4.0 or 5.0 Specifications.
    • Supports HBM devices compliant with JEDEC HBM DRAM Standard JESD235, JESD235A, JESD235B and JESD235C.
    • Supports all Interface Groups.
    • Supports Write Transactions with Data mask
    Block Diagram -- HBM DFI Verification IP
  • HBM DFI Assertion IP
    • Specification Compliance
    • Compliant with DFI version 4.0 or 5.0 Specifications.
    • Supports HBM devices compliant with JEDEC HBM DRAM Standard JESD235, JESD235A, JESD235B and JESD235C.
    • Supports all Interface Groups.
    Block Diagram -- HBM DFI Assertion IP
  • LVDS and OpenLDI PHY
    • Silicon proven with maximum speed @1.5Gbps per lane
    • Suitable for Automotive applications with ESD levels: HBM > 4KV and CDM > 750V
    • LVDS TX PHY: 4-data lanes plus 1-clock lane with each lane can be individually turned off
    • Supports long-distance transmission: Capable of maintaining signal integrity over longer cable length
    Block Diagram -- LVDS and OpenLDI PHY
  • HBM Memory Controller
    • Low latency, high bandwidth
    • Supports HBM or DDRx memory types
    • 16 parallel access channels
    • Multi, independent internal queues
    Block Diagram -- HBM Memory Controller
  • HBM2E PHY V2 - TSMC N5
    • Complete HBM2/HBM2E IP solution, including PHY, controller and verification IP, reduces integration risk while minimizing time-to-market
    • 2.5D interposer expertise and reference designs
    • Supports 2.5D-based JEDEC standard HBM2/HBM2E SDRAMs with data rates up to 3200 Mbps
    Block Diagram -- HBM2E PHY V2 - TSMC N5
  • HBM2E PHY V2 - TSMC 7FF18
    • Complete HBM2/HBM2E IP solution, including PHY, controller and verification IP, reduces integration risk while minimizing time-to-market
    • 2.5D interposer expertise and reference designs
    • Supports 2.5D-based JEDEC standard HBM2/HBM2E SDRAMs with data rates up to 3200 Mbps
    Block Diagram -- HBM2E PHY V2 - TSMC 7FF18
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