Gigacom IP

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Compare 6 IP from 1 vendors (1 - 6)
  • CEI-6G-SR PHY
    • Low Risk
    • Excellent Interoperability
    • Superior Noise Immunity
    Block Diagram -- CEI-6G-SR PHY
  • XAUI PHY
    • Very low output jitter
    • Receiver equalization for enhanced jitter tolerance
    • Programmable TX levels with multiple post-cursor emphasis options
    • Automatic driver/receiver impedance calibration
    Block Diagram -- XAUI PHY
  • SATA 3 PHY
    • Serial ATA III Revision 3.3 compliant
    • Gen1i, Gen1m, Gen2i, Gen2m compliant
    • Gen1x, Gen2x compatible
    Block Diagram -- SATA 3 PHY
  • SerialLite PHY with PCS
    • Integrated PCS Layer
    • Low power & area
    • Test Silicon
    Block Diagram -- SerialLite PHY with PCS
  • ARM HSSTP PHY with Link Layer
    • ARM HS-STP v6.0
    • ARM Coresight DDI 0314H
    • Xilinx Aurora 8b/10b v2.2
    Block Diagram -- ARM HSSTP PHY with Link Layer
  • SATA PHY
    • Serial ATA II Revision 2.6 compliant
    • Gen1i, Gen1m, Gen2i, Gen2m compliant
    • Gen1x, Gen2x compatible
    • Initialization and power saving modes
    Block Diagram -- SATA PHY
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Semiconductor IP