GDDR6 PHY IP
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13
IP
from 4 vendors
(1
-
10)
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GDDR6 PHY IP for 12nm
- JEDEC JESD250 compliant GDDR6 support
- X16 mode, X8 mode, and pseudo-channel mode
- Low frequency RDQS mode support
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GDDR6 PHY for Samsung
- Derived from Cadence’s silicon-proven DDR, LPDDR, and high-speed SerDes designs
- Highest data rates with detailed system guidelines
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GDDR6 PHY for TSMC
- Single configuration supports one GDDR6 device per channel (coplanar) or two GDDR6 devices per channel (clamshell)
- Memory controller interface uses DFI 5.0-like standard with extensions for GDDR6
- Internal and external datapath loop-back modes
- Per-bit DFE, CTLE, and FFE equalization
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GDDR6 Memory PHY - TSMC 7nm
- JEDEC JESD250C standard compliant
- Advanced process node
- East-West and North-South orientation
- 2 channels @ 16 bits/channel
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GDDR6 Memory PHY - TSMC 5nm
- JEDEC JESD250C standard compliant
- Advanced process node
- East-West and North-South orientation
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LPDDR5X/5/4X/4 combo PHY at 12nm
- Compliant with JEDEC JESD209-5C for LPDDR5x/5/4x/4 with PHY standards
- Delivering up to 8533Mbps
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
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LPDDR5X/5/4X/4 PHY for 16nm
- Compliant with JEDEC standards for LPDDR5/4x/4 with PHY standards
- DFI 5.0 Interface Compliant
- Supports up to 4 ranks
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GDDR6 Memory Controller IP
- JEDEC GDDR6 standard JESD250B
- Fast frequency switching
- Flexible Configuration
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LPDDR5X/5/4X/4 PHY IP for 12nm
- Compliant with JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
- DFI 5.0 Interface Compliant
- Supports up to 4 ranks
- Multiple frequency states
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Denali Controller for GDDR6
- Compatible with GDDR6 devices compliant to JESD250a
- Supports advanced RAS features including SEC/DED ECC, error scrubbing, parity, etc.
