OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined to bring synergy for high performance and low latency. OPENEDGES' integrated IP solutions are market and silicon-proven, featuring advanced architectures and proprietary technologies that enable customers to shorten their design and verification processes.
The HBM3 OPHY utilizes state-of-the-art architecture in full custom analog mixed-signal design to overcome the problem of long-term impedance drift and clock phase drift, allowing impedance and clock phase updates without the need to interrupt data traffic. The programmable timing PHY boundary combines flexibility with analog precision, and the result is ultra low PHY read/write latency between OMC and the HBM3 DRAM without sacrificing performance.
At the system level, the HBM3 OPHY was designed with minimal package substrate layer and PCB layer count in mind. This enables the integration of a HBM3 memory sub-system solution in cost sensitive applications, such as consumer edge devices, AI, GPU, HPC, STB, SSD controllers, and application processors.
HBM3 PHY IP at 7nm
Overview
Key Features
- Compliant with JEDEC JESD238 HBM3
- DFI5.1-based interface with memory controller
- Compliant with ESD requirements
- Supports up to 16-bit independent and asynchronous channel
- Delivering up to 8.4Gbps data rates per IO in a 2.5D integration platform
- Programmable TX drive strengths and RX DFE improves WRITE and READ eye margins
- Optional integrated memory controller
- Firmware-based BIST to assist with diagnostic and characterization
- Firmware-based PHY independent initialization of DRAM and training
- DCDL and PLL measurement
- Firmware-based training with proprietary microcontroller
- Internal loopbacks through datapath
- Supports DBI, ECC, SEV, and Parity (data and command/address parity)
- Autonomous lane repair
- Firmware-based API to work with DRAM's IEEE1500 for testing and training
Benefits
- Supports multiple PHY Frequency Set Points (FSPs) with fast switching time
- Multiple low-power states with fast exit time
- FW-based training and calibration provide flexibility and reduce PHY area
- PHY independent interconnect defect detection and lane repair
- Customizable FW-based BIST to improve observability and reduce bring-up time
- Automatic interconnect redundancy remapping
- Significantly reduce integration time and effort by providing hardened PHY channel
- Reference bump assignment allows optimal interposer routing
- Reference HBM3 signals routing on interposer available
- Fully integrated memory controller within each PHY channel
Block Diagram
Applications
- Provides an efficient solution for applications requiring high memory bandwidth, particularly in the fields of artificial Intelligence (AI), Machine Learning (ML), and general-purpose graphics processing units (GPGPU).
Deliverables
- Hard & Soft IP
- GDSII, LEF, LVS, timing models, etc.
- Verilog behavior models and encrypted RTL
- Synthesis and STA constraints
- Example test benches
- Documentation
- PHY Technical Reference Manual
- Implementation, package, and PCB design guidelines
- Test and characterization guidelines
- Physical verification reports
Technical Specifications
Foundry, Node
7nm
Maturity
Silicon-proven
Availability
Now