GDDR6 PHY IP for 12nm

Overview

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined to bring synergy for high performance and low latency. OPENEDGES' integrated IP solutions are market and silicon-proven, featuring advanced architectures and proprietary technologies that enable customers to shorten their design and verification processes.

The GDDR6 OPHY utilizes state-of-the-art architecture in full custom analog mixed-signal design to overcome the problem of long-term impedance drift and clock phase drift, allowing impedance and clock phase updates without interrupting data traffic. The programmable timing PHY boundary combines flexibility with analog precision, and the result is ultra-low PHY read/write latency between OMC and the GDDR6 DRAM without sacrificing performance.

The GDDR6 OPHY was designed at the system level with minimal package substrate layer and PCB layer count in mind. This enables the integration of a GDDR6 memory sub-system solution in cost-sensitive applications, such as consumer edge devices, AI, GPU, HPC, STB, SSD controllers, and application processors.

Key Features

DRAM supports
- JEDEC JESD250 compliant GDDR6 support
- X16 mode, X8 mode, and pseudo-channel mode
- Low-frequency RDQS mode support
High Performance
- Channel equalization with FFE, CTLE, and DFE
- Continuous IO impedance and timing phase updates with no traffic interruption
DFT Features
- IO internal/external loopback
- Integrated PRBS generator/checker
- IO bypass mode for internal clock observation
- Analog test ports for internal analog signals observation
Special Features
- PHY independent initialization of DRAM and training – no memory controller involved

Benefits

Configurability with Flexible Applications
- Configurable channel and floor plans allow connection to different DRAM package types and lane ordering
- Minimal package substrate/PCB layer requirements enable PHY usage in low-cost applications
Performance
- PSM enables accelerated firmware-based training
- Ultra-fast fractional training
- Programmable PHY boundary timing providing low read/write latency
- Fast switching between FSPs
Capacity
- Channel equalization and fast timing adjustment circuits enable four rank support to maximize capacity.
Power
- Power-saving modes with a variety of exit times
- Multiple voltage domains to optimize voltage versus frequency

Block Diagram

Applications

Consumer edge devices
Digital set-top-boxes
TVs
SSD controllers
Application processors

Deliverables

Hard & Soft IP
- GDSII, LEF, LVS, timing models, etc.
- Verilog behavior models and encrypted RTL
- Synthesis and STA constraints
- Example test benches
Documentation
- PHY Technical Reference Manual
- Implementation, package, and PCB design guidelines
- Test and characterization guidelines
- Physical verification reports

Technical Specifications

Foundry, Node

12nm

Maturity

Silicon Proven

Availability

Now

TSMC

In Production: 12nm
Pre-Silicon: 12nm
Silicon Proven: 12nm

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