IP Catalog > Interface IP > Memory Controller/PHY IP > DDR IP > DDR5 IP > DDR5 PHY IP > GDDR6X/6 Combo PHY & Controller

GDDR6X/6 Combo PHY & Controller

Overview

The GDDR6X/6 PHY is fully compliant with the JEDEC GDDR6X/6 standard, supporting data rates of up to 20Gbps per pin for PAM2 GDDR6 mode and 24Gbps for PAM4 GDDR6X mode. The GDDR6X/6 interface supports 2 channels, each with 16 bits for a total data width of 32 bits per memory device. With a maximum speed of 20/24Gbps per pin, The GDDR6X/6 Combo PHY delivers a peak bandwidth of up to 80GB/s or 96GB/s per memory device. Designed for advanced FinFET process nodes, this PHY is optimized for seamless integration into cutting-edge applications.

The comprehensive product portfolio also includes full GDS delivery, signal integrity and power integrity (SI/PI) analysis, verification models, prototyping support, and simulation tools. These offerings empower customers to accelerate development cycles, ensure robust performance, and stay ahead in the competitive landscape of high-performance memory solutions.

Key Features

  • Data rate up to 20Gbps (GDDR6) and 24Gbps (GDDR6X)
  • Pseudo open drain (POD‐135) compatible outputs
  • Driver strength and ODT auto calibration
  • PHY independent auto/software Command Address Training
  • PHY independent auto WCK2CK/Read/Write Training
  • PHY independent software Read/Write Training
  • PHY independent RX VREF Training
  • Supports WDBI/RDBI/CABI functions
  • Supports EDC QDR/DDR modes
  • Rx DFE for data inputs, with receiver characteristics programmable per pin
  • Supports both Write and Read CRC
  • Per bit Tx and Rx data phase delay and VREF adjustment
  • Internal high-performance low-jitter PLL
  • Tx de-emphasis EQ and Rx DFE EQ to improve signal integrity
  • Supports both Quad data rate (QDR) and double data rate (DDR) data (WCK) modes
  • Supports dynamic Read Training/Write Training with auto-refresh synchronization function
  • Accommodates Voltage/Temperature timing drift
  • Supports independent TX/RX/CMD delay line
  • Supports FR4 PCB material
  • Optional package/PCB design and SIPI analysis service
  • Supports Micron, Samsung, Hynix memory devices

Benefits

  • Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
  • Zero risk with robust ESD architecture
  • Extensive EDA tool support for various design and automation flow
  • Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self-refresh mode
  • Comprehensive observation registers DFX and methods are available to facilitate customers in identifying issues during testing

Block Diagram

GDDR6X/6 Combo PHY & Controller Block Diagram

Deliverables

  • Extensive documentation
  • Models
  • LIB
  • LEF
  • Place-and-route abstracts
  • LVS netlist
  • GDSII files

Technical Specifications

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