Denali Controller for GDDR6

Overview

GDDR6 devices to 16Gbps, 18Gbps, 20Gbps, and beyond

The latest, the Cadence Denali Controller IP for GDDR6, provides low latency and very high bandwidth, while supporting extensive value-added features including, but not limited to reliability features. Developed by experienced teams with industry-leading domain expertise and based upon Cadence’s widely proven DDR controller IP, the Controller IP for GDDR6 can provide customers with ease of integration and fast time-to-market. The Controller IP is engineered to quickly and easily integrate into any system-on-chip (SoC), and is verified with the Cadence Denali PHY IP for GDDR6 as part of a complete memory subsystem solution that also includes Cadence Verification IP (VIP). The Controller IP is designed to connect seamlessly and work with Cadence or thirdparty DFI-compliant PHY IP. Developed for and available in alignment with the PHY IP on advanced semiconductor process nodes, the Controller IP is designed to be robust under various traffic loads and to have interoperability with various supplier memory chips. The Controller IP is part of the comprehensive Cadence Design IP portfolio comprised of Denali memory interface, analog, and systems and peripherals IP.

Key Features

Compatible with GDDR6 devices compliant to JESD250B
Supports in-line ECC
Flexible paging policy including auto-prechargeper-command
Single and multi-port host interface options
Supports advanced RAS features including SEC/DED ECC, error scrubbing, parity, etc.
Priority-per command on Arm® AMBA® 3 AXI and low-latency Denali interface
QoS features allow command prioritization on Arm AMBA 4 AXI interfaces

Block Diagram

Applications

Data Processing

Deliverables

Clean, readable, synthesizeable Verilog RTL
Synthesis and STA scripts
Documentation—integration and user guide, release notes
Sample verification testbench with integrated BFM and monitors

Technical Specifications

Maturity

Silicon proven

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