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GDDR6 PHY

Overview

High-performance IP for graphics, AI/ML, and automotive products

The silicon-proven GDDR6 PHY and controller IP showcase leading-edge BER, BIST, and RAS capabilities. GDDR6 offers significantly more performance than the fastest speed of DDR5 at a moderate cost, making it ideal for high-bandwidth applications. Cadence’s unique, single-vendor GDDR6 IP solution speeds up integration and reduces interoperability risk.

Key Features

  • Single configuration supports one GDDR6 device per channel (coplanar) or two GDDR6 devices per channel (clamshell)
  •  DFI PHY Independent Mode for initialization and training
  • Adaptive and continuous timing recovery
  •  Internal and external datapath loop-back modes
  •  Transmit crosstalk cancelation of immediate neighbors
  •  Per-bit DFE, CTLE, and FFE equalization

Block Diagram

GDDR6 PHY Block Diagram

Deliverables

  • Fully-characterized hard macro (GDSII)
  • Complete design views
  • Full documentation

Technical Specifications

Maturity
Available on request
TSMC
Pre-Silicon: 5nm
Request Info

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