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Compare 67 IP from 26 vendors (1 - 10)
  • 32-512 Point Streaming FFT
    • Supports 32/64/128/256/512-point complex FFT and IFFT and can switch dynamically
    • Inputs and outputs data in the natural order
    • Throughput of 1 sample (In-phase I + quadrature Q) per 4 clocks; no-gap processing of the input data
    • Parameterized bit width.
    Block Diagram -- 32-512 Point Streaming FFT
  • Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
    • FFT size: Any size power-of-two or non-power-of-two
    • Dynamic Range: IEEE754 single precision floating point
    Block Diagram -- Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
  • Fixed-size streaming FFT
    • High Throughput: obtained from high clock rates (>500MHz using 65nm technology) and novel algorithms
    • FFT size: Any size power-of-two or non-power-of-two
    • Dynamic Range: combined block floating point and floating point architecture means smaller word lengths can be used for post processing operations such as equalization (~6db/bit).
    • Scalability: array based architecture means higher throughputs are obtained by increasing array size
    Block Diagram -- Fixed-size streaming FFT
  • Variable FFT (run time choice of FFT size)
    • High Throughput: obtained from high clock rates (>500MHz using 65nm technology) and novel algorithms
    • FFT size: any user chosen set of power-of-two or non-power-of-two sizes chosen at run-time (e.g., 128/256/512/1024/2048 points for LTE/WiMax OFDMA)
    • Programmability: Simple control circuitry for matching circuit/application functionality and I/O interface.
    • Dynamic Range: combined block floating point and floating point architecture means smaller word lengths can be used for post-processing operations such as equalization.
    Block Diagram -- Variable FFT (run time choice of FFT size)
  • FFT Compiler
    • Wide range of points sizes: 64, 128, 256, 512, 1024, 2048, 4096, 8192, and 16384
    • Choice of high-performance (streaming I/O) and low resource (burst I/O) versions
    • Run-time variable FFT point size
    • Forward, inverse or port-configurable forward/inverse transform modes
    Block Diagram -- FFT Compiler
  • High performance FFT with Gsps throughput
    • Throughput of greater than 8Gsps with 1GHz core clock frequency
    • Architecture can be scaled to support higher throughput per clock cycle
    • Configurable to supports large transform sizes i.e >8k
  • Fast Fourier Transformation
    • The FFT is a fully customizable FFT. The key features are free choose of the FFT dimension, data width and an additional output with the absolute value of the spectrum.
  • High performance FFT optimised for Radar
    • 1 clock cycle per point, no gap required between packets
    • Run-time selection of any power of 2 FFT points
    • Run-time selection of froward or inverse transform
  • Streaming pipelined FFT
    • 1 clock cycle per point, no gap required between packets
    • Run-time selection of any power of 2 FFT points
    • Run-time selection of forward or inverse transform
    • Internal convergent rounding
  • 32/64/128/256/512/1024/2048/4096 Point FFT Core
    • Supports 32/64/128/256/512/1024/2048/4096 point complex FFT and IFFT and up to 8192 point real-to-complex and complex-to-real FFT and IFFT and can switch dynamically. The real-to-complex and complex-to-real FFT/IFFT does not require any additional memory.
    • Built-in bit reversal. Outputs in natural order
    • Supports reading output data in any order (read address)
    • Low Latency. Can be customized to improve latency vs. gate count
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