Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs

Overview

This circuit uses Altera’s new Arria and Stratix 10 FPGAs with hardwired support for floating-point operations (IEEE754). Since Centar's FFT engine consists only of floating-point primitives (add, accumulate, multiply), there is a substantial reduction in LUT and register usage. Thus, high precision FFTs no longer use substantial FPGA resources, e.g., x2 and x6 less LUT/register usage compared to Centar's and Altera's fixed-point FFT IEEE754 implementation. Also, our Arria 10 versions use x2 fewer ALMs than Altera's. Finally, the locality, simplicity and regularity of the processing core keeps interconnect delays lower than cell delays, leading to reduced power dissipation and much higher throughputs.

Key Features

Applications: Eliminates design costs and time required to create custom fixed--point circuitry
Implementation: Using Altera Arria 10 and Stratix 10 FPGAs, LUT/register usage reduced by up to x6
FFT size: Any size power-of-two or non-power-of-two
Dynamic Range: single precision floating point
Scalability: Array based architecture means higher throughputs are obtained by increasing array size
Power: Array interconnects are entirely local, reducing parasitic routing capacitance to keep power dissipation low and clock speed high
Data I/O: Streaming, normal order I/O; IEEE754 standard words

Benefits

Programmable architecture easily modified to meet application requirements
Combined non-power-of-two and power-or-two options
Fastest commercially available throughputs
Minimal FPGA hardware resource usage
Run-time selection forward/inverse

Block Diagram

Applications

Radar imaging, medical imaging, industrial measurement, process control, high performance computing, advanced noise cancellation, high precision signal processing, signal intelligence

Deliverables

Netlist (e.g., for Altera FPGAs a *.qxp file for synthesis; a *.vo file or Modelsim library file for simulation)
Synthesis constraints (e.g., for Altera FPGA’s an *.sdc file)
Modelsim Testbench (*.vo file for DFT circuit plus verilog testbench for control). Matlab verification utilities also available.
Matlab behavioral bit-accurate model (p-code)
Documentation

Technical Specifications

Maturity

Verified

Availability

Now

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