Single precision fixed-size streaming floating-point FFT

Overview

This FFT circuit employs unique architectural characteristics providing functionality and capabilities not possible with other FFT implementations. Consequently, floating-point capability is obtained with the LUT/register and memory resources usually associated with lower precision fixed-point designs. For example a 1024-point design uses only ~6662 ALM's vs ~12883 for Altera's equivalent FFT, yet precision is x2 better. Additionally, the locality, simplicity and regularity of the processing core keeps interconnect delays lower than cell delays, leading to reduced power dissipation.

Key Features

  • FFT size: Any size power-of-two or non-power-of-two
  • Dynamic Range: IEEE754 single precision floating point
  • Scalability: Array based architecture means higher throughputs are obtained by increasing array size
  • Power: Array interconnects are entirely local, reducing parasitic routing capacitance to keep power dissipation low and clock speed high
  • Implementation FPGA: Centar's DFT circuit can be used in any FPGA fabric containing embedded multipliers and memories.
  • Data I/O: Streaming, normal order I/O
  • Input: fixed-point or IEEE754 sigle precision

Benefits

  • Programmable architecture easily modified to meet application requirements
  • Combined non-power-of-two and power-or-two options
  • Fastest commercially available throughputs
  • Minimal FPGA hardware resource usage
  • Run-time selection forward/inverse

Applications

  • Radar imaging, medical imaging, industrial measurement, process control, high performance computing, advanced noise cancellation, high precision signal processing, signal intelligence

Deliverables

  • Netlist (e.g., for Altera FPGAs a verilog *.qxp file for synthesis or *.vo file for simulation)
  • Synthesis constraints (e.g., for Altera FPGA’s an *.sdc file)
  • Modelsim Testbench (*.vo file for DFT circuit plus verilog testbench for control). Also includes Matlab verification utilities
  • Altera Stratix III FPGA board development kit testbench
  • Matlab behavioral bit-accurate model (p-code) for LTE FFT transform sizes
  • Documentation for above

Technical Specifications

Maturity
Verified
Availability
Now
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Semiconductor IP