IP Catalog > Ethernet Packet Processor

Ethernet Packet Processor IP

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Compare 27 IP from 8 vendors (1 - 10)
  • UCIe Die-to-Die Controller IP
    • High Configurability and Customizability
    • Comprehensive Verification
    Block Diagram -- UCIe Die-to-Die Controller IP
  • HiGig Ethernet MAC
    • Compliant to the Broadcom HiGig and HiGig2 Protocol Definitions
    • 64-bit wide internal data path operating at a maximum frequency of 187.5 MHz (LatticeECP3 maximum 156 MHz)
    • XGMII interface to the PHY layer (using IODDR external to the core)
    • XAUI interface to the PHY layer (using PCS/SERDES external to the core)
    Block Diagram -- HiGig Ethernet MAC
  • 10G/25G UDP/IP Hardware Protocol Stack
    • Complete UDP/IP Hardware Stack
    • Trouble-Free Network Operation
    • Run time programmable network parameters:
    • Local MAC address, Local IP address, Gateway IP address, and IP subnet mask
    Block Diagram -- 10G/25G UDP/IP Hardware Protocol Stack
  • 100G UDP/IP Hardware Protocol Stack
    • Complete UDP/IP Hardware Stack
    • Trouble-Free Operation
    • Easy SoC Integration
    Block Diagram -- 100G UDP/IP Hardware Protocol Stack
  • 40G/50G UDP/IP Hardware Protocol Stack
    • Complete UDP/IP Hardware Stack
    • Trouble-Free Network Operation
    • Run time programmable network parameters:
    • Local MAC address, Local IP address, Gateway IP address, and IP subnet mask
    Block Diagram -- 40G/50G UDP/IP Hardware Protocol Stack
  • UDP/IP Hardware Protocol Stack
    • Complete UDP/IP Hardware Stack
    • 10/100/1000 Ethernet
    • IPv4 support without packet fragmentation
    • Jumbo and Super Jumbo Frames
    Block Diagram -- UDP/IP Hardware Protocol Stack
  • 2.5Gbps Ethernet MAC IP Core
    • Compliant to IEEE 802.3-2005 standard
    • Generic 8-bit host interface
    • 16-bit wide internal data path
    • Generic transmit and receive FIFO interface
    Block Diagram -- 2.5Gbps Ethernet MAC IP Core
  • 2.5Gb Ethernet MAC
    • Compliant to IEEE 802.3z standard
    • Generic 8-bit host interface
    • 8-bit wide internal data path
    • Generic transmit and receive FIFO interface
    Block Diagram -- 2.5Gb Ethernet MAC
  • Hardware RTP Stack for JPEG Stream Encapsulation
    • RTP Encapsulation For JPEG Streams
    • Easier Integration For Faster Development
    Block Diagram -- Hardware RTP Stack for JPEG Stream Encapsulation
  • SPI4.2
    • The Soft SPI4 IP core is fully compliant with the OIF System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1) interface standard
    • Supported through Diamond or ispLEVER IPexpress™ tool for easy user configuration and parameterization
    • Supports up to 256 independent channels
    • 400 to 500MHz DDR Dynamic mode operation in LatticeSC and LatticeSCM devices
    Block Diagram -- SPI4.2
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