Ethernet IP

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Compare 990 IP from 101 vendors (1 - 10)
  • 100G Ethernet Verification IP
    • The 100G Ethernet Verification IP (VIP)  offers a robust and high-performance solution for validating the critical MAC-to-PCS datapath in 100 Gigabit Ethernet systems.
    • Designed to ensure protocol compliance, the VIP facilitates the generation, transmission, reception, and monitoring of various Ethernet MAC frame types, all while adhering to IEEE 802.3ba and related standards.
    • Whether you are working on IP, subsystem, or SoC-level verification, this VIP is your go-to solution for comprehensive Ethernet testing.
    Block Diagram -- 100G Ethernet Verification IP
  • Ethernet Controller
    • The Ethernet Controller is an ASIC proven high-performance, feature-rich network interface solution designed to deliver reliable, low-latency Ethernet connectivity across a broad range of embedded and enterprise applications.
    • Comcores offers controllers ranging from 10M to 800G enabling seamless integration into systems requiring Ethernet connectivity.
    Block Diagram -- Ethernet Controller
  • Ethernet PCS 1G/2.5G/5G/10G/25G & CPRI 7.0
    •  A combined silicon agnostic implementation of the PCS layer compliant with Ethernet standard IEEE 802.3-2018 and CPRI Specification V7.0 based solution
    • The IP-core supports 1G, 2.5G, 5G, 10G, and 25G Ethernet data rates as well as CPRI data rate option 1 (614.14M) to option 10 (24.33024G).
    Block Diagram -- Ethernet PCS 1G/2.5G/5G/10G/25G & CPRI 7.0
  • Ethernet PCS 800G
    • The 800G Ethernet PCS IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) described in the Ethernet standard IEEE 802.3-2020 and is compliant with Clause 170 and Clause 172 of the IEEE 802.3df specification.
    • 800G  Ethernet PCS IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a 32-lane parallel interface and offers an 800GMII interface on the other side.
    Block Diagram -- Ethernet PCS 800G
  • Ethernet PCS 200G/400G
    • The 200G/400G Ethernet PCS IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) described in the Ethernet standard IEEE 802.3-2020 and its compliant with Clause 117 and Clause 119 of IEEE 802.3 specification.
    • Ethernet PCS 200G/400G   IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a 8 or 16-lane parallel interface and offers a 200GMII or 400GMII interface on the other side.
    Block Diagram -- Ethernet PCS 200G/400G
  • Block Diagram -- Ethernet TSN MAC 40G/100G
  • Ethernet MAC 800G
    • The 800G Ethernet Media Access Control (MAC) IP core provides a comprehensive and flexible solution for implementing the IEEE 802.3 MAC layer for high-speed Ethernet required in demanding applications such as hyperscale data centers, high-performance computing (HPC), and Artificial Intelligence (AI) / Machine Learning (ML) clusters.
    Block Diagram -- Ethernet MAC 800G
  • Ethernet MAC 200G/400G
    • The 200G/400G Ethernet Media Access Control (MAC) IP core provides a comprehensive and flexible solution for implementing the IEEE 802.3 MAC layer for high-speed Ethernet required in demanding applications such as hyperscale data centers, high-performance computing (HPC), and Artificial Intelligence (AI) / Machine Learning (ML) clusters.
    Block Diagram -- Ethernet MAC 200G/400G
  • Deep Buffering Memory 1G Ethernet Switch
    • The 1G deep buffering memory Ethernet Switch is an advanced Ethernet switching IP that supports buffering large amounts of data in external RAM.
    • The non-blocking Ethernet switch IP core enables fine-grained traffic differentiation for rich implementations of packet prioritization, enabling per port and per queue shaping on egress ports.
    Block Diagram -- Deep Buffering Memory 1G Ethernet Switch
  • 10M/100M/1G/10G/25G Unmanaged Ethernet Switch
    • Unmanaged Ethernet Switch IP cores are a family of Ethernet switching IPs that provide a variety of port configurations, including 1G, 1G/10G, 10G, and 10G/25G options.
    • The unmanaged Ethernet switch IP cores family is a size-optimized implementation of non-blocking crossbar switches designed to support wire-speed packet processing and forwarding.
    Block Diagram -- 10M/100M/1G/10G/25G Unmanaged Ethernet Switch
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Semiconductor IP