ESIstream IP
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38
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from 13 vendors
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10)
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R-Tile PCIe Hard IP
- R-Tile is a FPGA companion tile that supports configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass modes
- PCIe 3.0, 4.0, and 5.0 configurations are natively supported
- R-Tile also supports up to 16 SerDes channels through a PHY Interface for PCIe (PIPE) 5.1.1 in SerDes Architecture mode.
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Intel® FPGA IP for PCIe
- PCI Express (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 gigatransfers per second (GT/s) to 32 GT/s and beyond
- Intel® FPGA Intellectual Property (IP) for PCIe continues to scale as the PCI-SIG organization delivers next-generation specifications
- Intel has been a member of PCI-SIG since 1992, and with each new generation of silicon, Intel continues to participate in PCI-SIG Compliance Workshops to ensure interoperability and conformance with current industry standards.
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Multichannel DMA Intel FPGA IP for PCI Express*
- The Multichannel DMA IP for PCI Express provides high efficiency, speed, and configuration flexibility to support various applications from HPC, cloud, networking, to embedded
- With support for up to 2048 channels and Linux-based PCIe drivers provided, this low latency, low resource utilization solution is essential in handling movements of large volumes of data to optimize system performance.
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AMBA AXI STREAM Verification IP
- Compliant with AMBA® AXI5- Stream and AXI4-Stream.
- Support for all types of AMBA AXI5-Stream and AXI4-STREAM components.
- Supports parameterized data widths.
- Supports byte stream transmission number of data and null bytes.
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AHB/AXI4-Lite to AXI4-Stream Bridge
- The MM2ST IP core bridges the streaming interfaces of a peripheral or accelerator to a memory-mapped AMBA® AHB or AXI4-Lite bus.
- Designed for ease of integration, it optionally implements clean clock-domain crossing (CDC) boundaries, allowing the peripheral and host system to operate in different clock domains.
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HBM Memory Controller
- Low latency, high bandwidth
- Supports HBM or DDRx memory types
- 16 parallel access channels
- Multi, independent internal queues
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LZ4/Snappy Data Decompressor
- LZ4SNP-D is a custom hardware implementation of a lossless data decompression engine for the LZ4 and Snappy compression algorithms.
- The core receives compressed files, automatically detects the LZ4 or Snappy format, and outputs the decompressed data.
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AXI4 to/from AXI4-Stream DMA
- The AXI4-DMA IP core implements a Direct Memory Access (DMA) engine that efficiently moves data between AXI4-Stream peripherals and a memory-mapped AXI4 bus.
- The core implements two independent paths: One transfers data from the read manager memory-mapped interface to the manager stream (MM2S) interface.
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I2S/TDM Multichannel Audio Transceiver
- The I2S-TDM IP core is a highly configurable, full-duplex, multichannel serial audio transceiver.
- The transceiver can act as a controller (master) or a target (slave) for Inter-IC Sound (I2S) and Time-Division Multiplexed (TDM) audio interfaces, exchanging mul-ti-channel audio samples over a configurable number of serial lines (pins).
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Non-Coherent Network-on-Chip (NOC)
- Node Protocols: AXI4, AXI5, AXI-Stream, APB and proprietary protocols
- Architected to reduce routing congestion and to ease high frequency timing closure
- Supports operating frequencies up to 2GHz
- Supports source synchronous and synchronous clocking topologies