Distortion Correction IP

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Compare 18 IP from 11 vendors (1 - 10)
  • Image warping IP (Distortion Correction IP)
    • Resolution: Up to 16K x 16K
    • Input/output images: Different RGB/YUV formats, 8 or 10-bit color
  • Image warping IP (distortion correction IP)
    • Resolution: Up to 4K x 4K
    • Input/output images: Different RGB/YUV formats, 8-bit color
    • Functions: Distortion correction (any-shape transform), scaling, rotation
  • DAC Correction Filter
    • Efficient, multiplier-free design
    • Configurable input and output widths
    • Multiple tap-length configurations
    Block Diagram -- DAC Correction Filter
  • Video and Vision Processing Suite
    • The Intel® FPGA Video and Vision Processing Suite is a collection of next-generation Intel® FPGA intellectual property (IP) functions that you can use to facilitate the development of custom video and image processing designs
    • These Intel® FPGA IP functions are suitable for use in a wide variety of image processing and display applications, such as studio broadcast, video conferencing, AV networking, medical imaging, industrial inspections and robotics, smart city/retail and consumer.
    Block Diagram -- Video and Vision Processing Suite
  • Image Signal Processor (5MP, 2X Sensors) IP
    • Self-contained, no external memory needed
    • ARM® Cortex-R4 CPU @500 MHz
    • Up to 2 Mbytes of SRAM
    • Up to 4 Mbytes of stacked Flash or 16 Mbyte external Flash with update via communication interfaces
    Block Diagram -- Image Signal Processor (5MP, 2X Sensors) IP
  • HDR Image Signal Processor
    • Advanced motion compensation algorithms virtually eliminate HDR merge artifacts and transition noise
    • Proprietary Locally Adaptive Tone Mapping technology
    Block Diagram -- HDR Image Signal Processor
  • DeWarp Processor IP
    • DeWarp Engine Features
    • Video Scaling Engine Features
    • Option add-on Features
  • DeWarp Processor IP - High Performance DeWarp Processing
    • Fisheye correction
    • Wide Field of View (FOV) correction
    • Keystone correction
    • Scaling up from 1x to 4x, apply in DeWarp images
  • DVB-T/DVB-H modulator
    • Fully compliant with ETSI EN 300 744 V1.5.1.
    • Extension core available for DVB-T(H) support.
    • Enables rapid development of audio/visual systems using commodity Free-to-Air set-top-box technology and low-cost FPGAs.
    • Configurable support for 2K and 8K OFDM modes and hierarchical transmission. (4k for DVB-T(H))
    Block Diagram -- DVB-T/DVB-H modulator
  • DVB-CID modulator
    • The CMS0069 DVB-CID Modulator provides all the necessary processing steps to modulate the Content-ID table into a complex I/Q signal for input to a pair of DACs, or interpolating DAC devices such as the AD9857/AD9957 or RF DACs such as the AD9789. Optionally the output can be selected as an IF to supply a single DAC.
    • The design has been optimised to provide excellent performance in low cost FPGA devices such as the Cyclone range from Altera or the Spartan range from Xilinx
    Block Diagram -- DVB-CID modulator
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Semiconductor IP