The proliferation of low-cost DVB-T/DVB-H demodulation and set-top-box products has opened up a wealth of opportunities for applications requiring low-cost broadband wireless audio/video/data links. Commodity products have largely been aimed at the broadcast market where the high volumes are at the demodulation end of the link. The Commsonic DVB-T Modulator allows exploitation of this technology by allowing the development of the modulator in low-cost FPGA or ASIC implementation. Applications include CCTV, wireless home networking, test equipment, etc.
This core is intended to provide a very efficient FPGA or ASIC implementation of all functions required to take the output from an MPEG-2 transport multiplexer and modulate it according to ETSI EN300 744 v1.5.1. The specification is fully supported for 2K, 4K and 8K COFDM modes as well as hierarchical transport streams. The standard output is a baseband I/Q digital pair for direct connection to a DAC. Alternative output configurations include a low IF or direct connection to standard Analog Devices Direct Digital Synthesizers (e.g. AD9857).
Every effort has been made to keep the size of the block to an absolute minimum in order to target the low-cost FPGA families, however this has not been at the expense of functionality. Synthesis directives are used wherever possible to remove a block within the design has functionality that may not be required for all applications.
DVB-T/DVB-H modulator
Overview
Key Features
- Fully compliant with ETSI EN 300 744 V1.5.1.
- Extension core available for DVB-T(H) support.
- Enables rapid development of audio/visual systems using commodity Free-to-Air set-top-box technology and low-cost FPGAs.
- Configurable support for 2K and 8K OFDM modes and hierarchical transmission. (4k for DVB-T(H))
- Variable channel bandwidth support using a single clock reference; 5MHz… 8MHz.
- AD9857 interface and auto-programming support.
- Optional dual-core combining into the AD9857 for multi-channel applications.
- Extension core available for SPI/ASI interface with integrated PCR TS re-stamping, NULL TS packet removal/filtering, NULL/PRBS TS packet insertion, input and output TS rate estimation registers.
- Seamless integration with Altera ASI megacore when using SPI/ASI extension core.
- Optional FFT output windowing.
- Optional critical-mask output filtering.
- Modes that are not required may be removed with synthesis options to generate a compact, efficient design.
- Designed for very efficient FPGA implementation without compromise to the targeting of gate array or standard cell structures.
- Supplied as a protected bitstream or netlist (megacore for Altera FPGA targets).
Deliverables
- Evaluation boards available
Technical Specifications
Availability
now