Display Port/eDisplay Port IP
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513
IP
from 65 vendors
(1
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10)
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VDC-M (VESA Display Compression-M) Decoder
- VESA Display Compression-M (VDC-M) 1.1 compliant
- Supports all VDC-M encoding mechanisms
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VDC-M (VESA Display Compression-M) Encoder
- VESA Display Compression-M (VDC-M) 1.1 compliant
- Supports all VDC-M encoding mechanisms
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VESA DSC (Display Stream Compression) 1.2b Video Decoder
- VESA DSC 1.2 compliant
- Supports all DSC 1.2 mandatory encoding mechanisms
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VESA DSC (Display Stream Compression) 1.2b Video Encoder
- VESA DSC 1.2 compliant
- Supports all DSC 1.2 mandatory encoding mechanisms
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Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
- eDP version 1.4a / DP version 1.4 compliant transmitter
- Supports HDCP1.4 and HDCP2.2(Optional)
- Supports Forward Error Correction (Optional)
- Consists of configurable (4/2/1) link channels and one AUX channel
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VESA Display Stream Compression (DSC) IP Core
- Supports Versions 1.1, 1.2 and 1.2a
- Supports RGB and YCbCr color spaces
- 1-to-8 slice support
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Display Stream Compression (DSC 1.2) Encoder
- VESA DSC 1.2 Compliant
- Capable of encoding up to 4K video at 30fps in FPGA and ASIC
- 8K compression available for select applications
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Display Stream Compression (DSC 1.2) Decoder
- VESA DSC 1.2 Compliant
- Capable of decoding 4K video at 30fps in FPGA and ASIC
- Decode 8K video at 30fps in ASIC applications
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TFT/LCD/MIPI Display Controller and Composition Engine
- Programmable display resolutions up to 32Kx32K
- Compressed framebuffer support
- Variable Frame-Rate support
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Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 55SP
- DisplayPort version 1.4 compliant receiver
- PHY supports 1.62Gbps (RBR) to 5.4Gbps (HBR2) bit rate
- Integrated 100-ohm termination resistors with common-mode biasing
- Integrated equalizer with tunable strength
