Embedded Display Port Verification IP

Overview

Embedded Display port is the serial communication protocol developed by Video Electronics Standards Association to support the video,audio and other data between a source device and sink device. Embedded Display port VIP can be used to verify transmitter or Receiver device following the Embedded Display port basic protocol as defined in Embedded Display port.

Embedded Display Port Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Embedded Display Port Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Full Embedded Display port source device and sink device functionality.
Embedded Display port v1.3,1.4,1.4b and 1.5 compliant and based on display port specs 1.2/1.2a/1.3/1.4/2.0.
Support transmitter and receiver Mode.
Supports multi lanes upto 4 lanes.
Supports main link, Aux link and Hot plug functionality.
Supports packing of all the video formats supported by the display port.
Supports HPD based link training.
Supports interlane skew insertion in transmitter mode.
Supports deskew in sink device mode.
Supports scrambler as in Display port specification.
Scrambler can enabled or disabled dynamically.
Supports scrambler reset after every 512th symbols.
Support on the fly generation of data.
Supports High-bandwidth Digital Content Protection System version1.3 (HDCP v1.3)
Supports High-bandwidth Digital Content Protection System version2.2 (HDCP v2.2)
- Supports for HDCP2.2 with full authentication.
- Supports for HDCP2.2 with bypass the authentication.
Supports High-bandwidth Digital Content Protection System version2.3 (HDCP v2.3)
Detects and reports the following errors,
- Invalid control character
- Invalid data character
- Invalid 10bit code
- Sync errors
- Scrambler errors
Supports ECC.
Single and multi bit ECC errors.
Invalid packing injection and detection.
Supports PSR(Panel Self Refresh) entry and exit.
Supports Selective update (partial frame update) during Panel Self Refresh (PSR).
Supports PSR2(Panel Self Refresh) as per spec eDPv1.5
Supports Multi SST operation(MSO)
- Two SST Links with one Lane each (two Lanes total), 2x1
- Two SST Links with two Lanes each (four Lanes total), 2x2
- Four SST Links with one Lane each (four Lanes total), 4x1
Supports Advanced Link Power Management to reduce wake latency.
Supports GTC-based video timing synchronization.
Supports Display stream compression as per spec eDPv1.5
Supports Forward Error Correction as per spec eDPv1.5
Supports PSR Secondary Data Packet.
Supports Display Backlight Control Using DPCD Registers.
Supports frame number identification in PSR.
Monitors, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Status counters for various events on bus.
Embedded Display port Verification IP comes with complete testsuite to test every feature of eDP specification.
Functional coverage for complete eDP features.
Supports constraints Randomization.
Callbacks in node transmitter, receiver and monitor for user processing of data.

Benefits

Faster testbench development and more complete verification of Embedded Display port designs.
Easy to use command interface simplifies testbench control and configuration of receiver and transmitter.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the Embedded Display port testcases.
Examples showing how to connect various components, and usage of Transmitter, Receiver and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation contains User's Guide and Release notes.

Technical Specifications

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