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DMA Engine IP

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Compare 189 IP from 50 vendors (1 - 10)
  • Multi-Channel AXI DMA Engine
    • The Multi-Channel AXI DMA engine IP Core for AXI4 is a powerful programmable AXI Stream to AXI memory mapped bridge with sophisticated data addressing options.
    • These features allow data accesses on a tile basis in order to address regions of interest (ROI) based applications like stereo cameras, 2D picture compression algorithms and others.
    Block Diagram -- Multi-Channel AXI DMA Engine
  • Scatter Gather DMA Engine - Validates efficient scatter-gather DMA for high-performance data transfer
    • The Scatter-Gather DMA Engine Verification IP (VIP) is designed to validate the functionality and performance of scatter-gather DMA controllers in SoCs. It ensures efficient data transfer between non-contiguous memory regions while minimizing CPU utilization, offering features like protocol compliance and transaction monitoring.
    • Ideal for applications such as networking, multimedia, storage, and embedded systems, the VIP helps ensure high-performance, reliable data movement. It supports multi-channel configurations, error injection, and performance monitoring to optimize system efficiency and robustness
    Block Diagram -- Scatter Gather DMA Engine - Validates efficient scatter-gather DMA for high-performance data transfer
  • Lancero Scatter-Gather DMA Engine for PCI Express
    • PCIe I/O performance: 200 MB/s x1 Gen 1 up to 3360 MB/s x8 Gen 2
    • Easily connect logic and high-speed I/O peripherals to PCI Express
    • Target Bridge supports Avalon Memory Mapped custom logic
    • SGDMA Engine supports Avalon Streaming burst access devices
    Block Diagram -- Lancero Scatter-Gather DMA Engine for PCI Express
  • Cryptographic engine using the DES, Triple-DES or AES
    • The cryptographic processor (CRYP) can be used both to encrypt and decrypt data using the DES, Triple-DES, AES or SM4 algorithms.
  • Security Hash, SM3 Hash and HMAC Engine
    • The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512), the MD5 (message-digest algorithm 5) and SM3 hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications. HMAC is suitable for applications requiring message authentication.
  • AHB AES with DMA
    • The Advanced Encryption Standard (AES) IP Core is a complete hardware implementation encryption/decryption algorithm described in the U.S. Government Federal Information Processing Standards Publication 197 (FIPS 197).
    • The AES IP Core implements the Rijndael algorithm which is a symmetric block cipher that can process 128-bit data blocks using 128, 192, or 256-bit cipher keys.
    Block Diagram -- AHB AES with DMA
  • AHB/AXI/Wishbone DMA Controller
    • The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the host system with an AXI4 Memory-Mapped master port and the peripheral with either a slave or a master AXI4-Stream port.
    • The core operates in either Scatter-Gather (SG) Mode, reading descriptors from a run-time defined memory mapped-location, or in Direct Mode, transferring data according to a descriptor stored in local registers.
    Block Diagram -- AHB/AXI/Wishbone DMA Controller
  • DMA Controller with TileLink IIP
    • Supports 1-16 channel DMA Transmit and DMA Receive Engine
    • Compliant with TileLink specification v1.7.1
    • Supports access for Ring and Chained Descriptor Structures
    • Configurable Transmit and Receive Engine based on Host Memory Data Width
    Block Diagram -- DMA Controller with TileLink IIP
  • DMA Controller with OCP IIP
    • Supports 1-16 channel DMA Transmit and DMA Receive Engine
    • Compliant with OCP 3.1 specification
    • Supports access for Ring and Chained Descriptor Structures
    • Configurable Transmit and Receive Engine based on Host Memory Data Width
    Block Diagram -- DMA Controller with OCP IIP
  • DMA Controller with AXI IIP
    • Supports 1-16 channel DMA Transmit and DMA Receive Engine
    • Supports latest ARM AMBA 3/4 AXI, AXI4-Lite, AMBA4 ACE, AMBA4 ACE-Lite, AXI4-Stream specification.
    • Supports access for Ring and Chained Descriptor Structures
    • Configurable Transmit and Receive Engine based on Host Memory Data Width
    Block Diagram -- DMA Controller with AXI IIP
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