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DDR3 Memory Controller IP

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  • DDR3 Memory Controller
    • Maximizes bus efficiency via Look-Ahead command processing, Bank Management, Auto-Precharge and Additive Latency support
    • Minimal latency achieved via parameterized pipelining
    • Achieves high clock rates with minimal routing constraints
    • Supports full rate and half-rate clock operation
  • DDR3 PHY
    • Supports write leveling for each DQS group. Option to switch off write leveling for On-board memory applications
    • Supports all valid DDR3 commands
    • Supports dynamic On-Die Termination (ODT) controls
    • LatticeECP3 I/O primitives manage read skews (Read Leveling equivalent)
    Block Diagram -- DDR3 PHY
  • DDR3 SDRAM Memory Controller
    • Supports DDR3 SDRAM memory devices on AMD-Xilinx 7 Series FPGAs
    • Size optimized – ideal for low cost 7 Series FPGAs (Artix-7, Spartan-7)
    Block Diagram -- DDR3 SDRAM Memory Controller
  • DDR2 & DDR3 Fault Tolerant Memory Controller
    • Configurable to have multiple AHB ports with concurrent accesses to different memory banks
    • 96-, 64- or 32-bits interface towards SDRAM
    Block Diagram -- DDR2 & DDR3 Fault Tolerant Memory Controller
  • DDR 4/3 Memory Controller IP - 2400MHz
    • Support s DDR 4 /DDR3 SDRAM
    • 16 bit s width , Single Channel DDR 4 /DDR3 SDRAM Interface .
    • 16 bits for per channel, could support 2 x8 bits DDR3, but could not support 2 x8 bits DDR4.
    • Memory Clock up to 6 66 MHz, DFI Clock up to 666 MHz .
    Block Diagram -- DDR 4/3 Memory Controller IP - 2400MHz
  • DDR3 Controller IP
    • o High memory throughput achieved via Parallel operation of all the banks and reordering of commands in the controller to ensure the maximum utilization of the DDR Memory
    • o Pipelined operation across the complete design to ensure the highest performance
    • o DDR Interface
    • o Supports all standard DDR3 (x4,x8,x16) SDRAMs
  • DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
    • Support DDR3 / DDR3L / DDR4/ 3DS DDR4/ LPDDR4 / MRAM
    • Support x8/x16/x32 DRAM data bus configuration (programmable)
    • Support Multi-Ranks DRAM configuration
    • DDR base on DFI spec 4.0 compliant.
    Block Diagram -- DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
  • DDR3 SDRAM Controller
    • Support for all LatticeECP3 “EA” devices
    • Interfaces to Industry Standard DDR3 SDRAM components and modules compliant with JESD79-3, DDR3 SDRAM Standard
    • Interfaces to DDR3 SDRAM at speeds up to 400 MHz / 800 Mbps in -8 speed grade devices
    • Supports memory data path widths of -8, -16, -24, -32, -40, -48, -56, -64 and -72 bits
    Block Diagram -- DDR3 SDRAM Controller
  • High Performance DDR 3/2 Memory Controller IP
    • Supports DDR3/DDR2 SDRAM
    • 16 bits width DDR2/DDR3 SDRAM Interface
    • Memory Clock up to 462MHz, DFI Clock up to 462MHz
    • Support DDR2 667/800/1066 and DDR3 667/800/1066/1333/1600/1866
  • 10Gbit/s Ethernet UDT Server for FPGAs
    • High data rate: 10Gbit/s sustained data transfer to FPGA
    • Protocol processing in Xilinx Microblaze
    • Data handling in FPGA hardware offload logic
    • Compatible with the UDT4 library
    Block Diagram -- 10Gbit/s Ethernet UDT Server for FPGAs
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