Ddr2 phy IP

Compare 28 IP from 13 vendors (1 - 10)

DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process
DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process
DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process
DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process
DDR3/ DDR2 Combo PHY IP - 1866Mbps (Silicon Proven in UMC 40LP)
- Supports DDR3/DDR2 SDRAM
- DDR3 JEDEC standard 1.5v I/O (SSTL_15- compatible)
- DDR2 JEDEC standard 1.8v I/O (SSTL_18- compatible)
- 16 bits width, Single Channel DDR3/DDR2 SDRAM Interface.
DDR2 DFI Verification IP
- Compliant with DFI version 2.0 or higher Specification.
- DFI-DDR2 Applies to :
- DDR2 protocol standard JESD79-2F Specification
- Supports all Interface Groups.
DDR2 DFI Assertion IP
- Specification Compliance
- Compliant with DFI version 2.0 or higher Specification.
- DFI-DDR2 Applies to :
- DDR2 protocol standard JESD79-2F Specification
DDR3/2 PHY - TSMC 40LP25
- When combined with a Synopsys DDR memory or protocol controller and verification IP, Synopsys provides a complete DDR3/2 interface IP solution
- Scalable architecture that supports the speed range from DDR2-667 up to DDR3-2133
- Support for DDR3L (1.35V DDR3)
- Support for DDR2 and DDR3 DIMMs

DDR2 PHY IP