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DDR SDRAM PHY IP

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Compare 164 IP from 13 vendors (1 - 10)
  • SDRAM LPDDR5/4x/4/3/2 Host Controller & PHY - TSMC 16nm 16FFC,FF
    • DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
    • Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
    • Built-in Gate Training, Read/Write Leveling, and VREF Training
    • Multi-Port Configurable AXI4 Interface with QoS Signaling, Single AXI4-Lite Programming Interface
  • SDRAM DDRx & LPDDR4x Host Controller & PHY - TSMC 12nm 12FFC,FFC+
    • + DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
    • + Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
    • + Built-in Gate Training, Read/Write Leveling, and VREF Training
    • + Multi-Port Configurable AXI4 Interface with QoS Signaling, Single AXI4-Lite Programming Interface
  • SDRAM LPDDR5/4x/4/3/2 Host Controller & PHY
    • + DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
    • + Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
    • + Built-in Gate Training, Read/Write Leveling, and VREF Training
    • + Multi-Port Configurable AXI4 Interface with QoS Signaling, Single AXI4-Lite Programming Interface
  • SDRAM DDR4/3/2 Host Controller & PHY
    • + DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
    • + Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
    • + Built-in Gate Training, Read/Write Leveling, and VREF Training
    • + Multi-Port Configurable AXI4 Interface with QoS Signaling, Single AXI4-Lite Programming Interface
  • DDR3 Memory Controller
    • Maximizes bus efficiency via Look-Ahead command processing, Bank Management, Auto-Precharge and Additive Latency support
    • Minimal latency achieved via parameterized pipelining
    • Achieves high clock rates with minimal routing constraints
    • Supports full rate and half-rate clock operation
  • DDR4 Memory Controller
    • Maximizes bus efficiency via Look-Ahead command processing, Bank Management, Auto-Precharge and Additive Latency support
    • Minimal latency achieved via parameterized pipelining
    • Achieves high clock rates with minimal routing constraints
    • Supports half-rate and quarter-rate clock operation
  • DDR4 multiPHY in UMC (28nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard DDR4 up to 2667 Mbps
    • Compatible with JEDEC standard DDR3 SDRAMs up to 2133 Mbps
    • Compatible with JEDEC standard LPDDR2 SDRAMs up to 1066 Mbps
  • DDR4 multiPHY in TSMC (28nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard DDR4 up to 2667 Mbps
    • Compatible with JEDEC standard DDR3 SDRAMs up to 2133 Mbps
    • Compatible with JEDEC standard LPDDR2 SDRAMs up to 1066 Mbps
  • DDR4 multiPHY in Samsung (14nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard DDR4 up to 2667 Mbps
    • Compatible with JEDEC standard DDR3 SDRAMs up to 2133 Mbps
    • Compatible with JEDEC standard LPDDR2 SDRAMs up to 1066 Mbps
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