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D2D interconnect IP

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Search (9)
Compare 9 IP from 8 vendors (1 - 9)
  • Die-to-Die (D2D) Interconnect
    • Adaptable to any communication protocols including extending SkyeChip’s Non-Coherent and Coherent NOC interconnects across multiple dies
    • Architected to significantly reduce wiring overhead across multiple dies
    • Supports transfer rates of up to 6.4GT/s
    • Supports major 2.5D and 3D inter-die packaging technologies
  • D2D Controller addon for D2D SR112G PHY with CXS interface
    • Low Latency controller for die-to-die connectivity
    • Supports PAM-4 and NRZ PHY signaling mode in all data rates
    • Reduces BER with optional FEC configurations
    • Supports Arm® AMBA® CXS interface
    Block Diagram -- D2D Controller addon for D2D SR112G PHY with CXS interface
  • Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications
    • High data rate of 2–24 Gb/s
    • Very low power of < 0.375 pJ/bit @ 2–16 Gb/s 0.5-V VDDQ
    • Very low latency of < 2 ns PHY-to-PHY
    • Support for 2:1, 4:1, 8:1, 12:1 and 16:1 serialization and deserialization ratios
  • D2D UCIe 1.1
    • Compatible with UCIe v1.1 specification
    • Features single-ended, source-synchronous, and DDR I/O signaling
    • Supports 32-bit (16-bits TX + 16-bit RX) data bus per module for standard packages
    • Offers a high clock frequency up to 16GHz
    Block Diagram -- D2D UCIe 1.1
  • D2D UCIe 1.0
    • Compatible with UCIe v1.0 specification
    • Single-ended, source synchronous and DDR IO Signaling
    • Supports 32 bits(16bits TX + 16bits RX) data bus per module for standard package
    • High clock frequency, up to 8GHz
    Block Diagram -- D2D UCIe 1.0
  • IPTD2D-A PHY and Controller
    • Supports CoWoSTM, INFOTM and EMIBTM package technologies
    • Supports any speed ranging from 2Gbps to 16Gbps, achieving the best balance between total bandwidth and power consumption
  • Simulation VIP for UCIE
    • Protocol Layer Features
    • Streaming mode
    • PCIe mode
    • Protocol FDI LSMs
    Block Diagram -- Simulation VIP for UCIE
  • INNOLINK Chiplet PHY&Controller
    • Innolink-A
    • Meets the performance, efficiency and reliability requirements of B2B/C2C interconnects
    • Already silicon proven
    • Delivers 56Gbps/pair with -36dB insertion loss
  • 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
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Semiconductor IP