CXL 2.0 Controller IP

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Compare 22 IP from 9 vendors (1 - 10)
  • CXL 2.0 Controller with AXI
    • Supports the latest CXL specification
    • AMBA AXI Layer for CXL.io
    Block Diagram -- CXL 2.0 Controller with AXI
  • CXL 2.0 Controller
    • Internal data path size automatically scales up or down (256, 512 bits) based on max. link speed and width for reduced gate count and optimal throughput
    • Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
    • Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
    • Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs (when supported)
    Block Diagram -- CXL 2.0 Controller
  • CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge and Advanced HPC Features (Arm CCA)
    • Supports all required features of CXL 3.1 and CXL 3.0
    • Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
    • Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
    Block Diagram -- CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge and Advanced HPC Features (Arm CCA)
  • CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge + LTI and MSI-GIC interfaces
    • Supports all required features of CXL 3.1 and CXL 3.0
    • Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
    • Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
    Block Diagram -- CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge + LTI and MSI-GIC interfaces
  • CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge
    • Supports all required features of CXL 3.1 and CXL 3.0
    • Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
    • Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
    Block Diagram -- CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge
  • CXL 2.0 Premium Controller Device/Host/DM 512b
    • Supports all required features of CXL 3.1 and CXL 3.0
    • Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
    • Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
    Block Diagram -- CXL 2.0 Premium Controller Device/Host/DM 512b
  • CXL 2.0 Dual Mode Controller
    • Compatible with CXL 2.0 specification and backward compatible with CXL V1.0 and CXL V1.1
  • CXL Controller IP
    • The CXL/PCIe Controller IP carries out CXL 3.0 specification and is backward compatible to CXL 2.0 and 1.1.
    • Possessing high customizability and supportability, this controller provides a comprehensive CXL solution.
    Block Diagram -- CXL Controller IP
  • Compute Express Link (CXL) 1.1/2.0/3.0 Controller
    • Implements CXL 3.0 Specification at 64 GT/s
    • Parallel Multiple TLP/DLLP processing engine for best performance, throughput, and latency
    • Designed for easy integration with PipeCORE™ PCIe® PHY IP
    Block Diagram -- Compute Express Link (CXL) 1.1/2.0/3.0 Controller
  • CXL 2.0 Integrity and Data Encryption Security Module
    • Compliant with the CXL 2.0 IDE specifications for CXL.cache/mem
    • Compliant with PCI Express IDE specification for CXL.io
    • High-performance AES-GCM based packet encryption, decryption, authentication
    Block Diagram -- CXL 2.0 Integrity and Data Encryption Security Module
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