Binary BCH IP
Filter
Compare
3
IP
from
3
vendors
(1
-
3)
-
BCH Decoder IP
- BCH decoder compliant with the DVB-T2/S2 standard.
- Available for Altera/Xilinx FPGA or ASIC implementation.
- High speed design.
- BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
-
ECC with BCH Algorithm
- High bandwidth, low latency parallel encode and decode paths
- Configurable number of encode blocks
- Configurable number of decode blocks
- Configurable code word length (K), up to 1024 bytes
-
BCH Decoder
- BCH decoder compliant with the DVB-T2/S2 standard.
- Available for Altera/Xilinx FPGA or ASIC implementation.
- High speed design.
- BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
- Area and power optimized implementation.
