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Automotive PHY IP

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Search (226)
Compare 226 IP from 25 vendors (1 - 10)
  • MIPI D-PHY RX/TX v1.1 / v1.2 IP in TSMC (12/16nm, 28nm, 40nm, and 55nm process)
    • Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
    • Supports MIPI DSI and CSI-2 protocols
    • Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
    • Supports LS data rate of 10Mbps and Ultra-low power modes
  • MIPI DPHY_RX v1.2, 2C4D, UMC 28HPC+, E/W orientation
    • Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
    • Supports MIPI DSI and CSI-2 protocols
    • Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
    • Supports LS data rate of 10Mbps and Ultra-low power modes
    Block Diagram -- MIPI DPHY_RX v1.2, 2C4D, UMC 28HPC+, E/W orientation
  • MIPI DPHY_TX v1.2, 1C4D, UMC 28HPC+, E/W orientation
    • Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
    • Supports MIPI DSI and CSI-2 protocols
    • Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
    • Supports LS data rate of 10Mbps and Ultra-low power modes
    Block Diagram -- MIPI DPHY_TX v1.2, 1C4D, UMC 28HPC+, E/W orientation
  • MIPI DPHY_TX v1.1, 1C4D, TSMC 55LP
    • Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
    • Supports MIPI DSI and CSI-2 protocols
    • Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
    • Supports LS data rate of 10Mbps and Ultra-low power modes
    Block Diagram -- MIPI DPHY_TX v1.1, 1C4D, TSMC 55LP
  • MIPI DPHY_RX v1.1, 1C2D, TSMC 40ULP_EF
    • Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
    • Supports MIPI DSI and CSI-2 protocols
    • Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
    • Supports LS data rate of 10Mbps and Ultra-low power modes
    Block Diagram -- MIPI DPHY_RX v1.1, 1C2D, TSMC 40ULP_EF
  • MIPI DPHY_TX v1.1, 1C4D, TSMC 40UL_PEF
    • Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
    • Supports MIPI DSI and CSI-2 protocols
    • Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
    • Supports LS data rate of 10Mbps and Ultra-low power modes
    Block Diagram -- MIPI DPHY_TX v1.1, 1C4D, TSMC 40UL_PEF
  • MIPI DPHY_RX v1.1, 2C4D, TSMC 40LP
    • Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
    • Supports MIPI DSI and CSI-2 protocols
    • Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
    • Supports LS data rate of 10Mbps and Ultra-low power modes
    Block Diagram -- MIPI DPHY_RX v1.1, 2C4D, TSMC 40LP
  • MIPI DPHY_RX v1.2, 2C4D, TSMC 28HPC+, E/W orientation
    • Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
    • Supports MIPI DSI and CSI-2 protocols
    • Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
    • Supports LS data rate of 10Mbps and Ultra-low power modes
    Block Diagram -- MIPI DPHY_RX v1.2, 2C4D, TSMC 28HPC+, E/W orientation
  • MIPI DPHY_TX v1.2, 1C4D, TSMC 28HPC+, E/W orientation
    • Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
    • Supports MIPI DSI and CSI-2 protocols
    • Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
    • Supports LS data rate of 10Mbps and Ultra-low power modes
    Block Diagram -- MIPI DPHY_TX v1.2, 1C4D, TSMC 28HPC+, E/W orientation
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