LPDDR5X/5/4X PHY IP in SF5A for Automotive

Overview

The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackage applications requiring high-performance LPDDR5X, LPDDR5, and LPDDR4X SDRAM interfaces operating at up to 8533 Mbps. With flexible configuration options, the LPDDR5X/5/4X PHY can be used in a variety of mobile applications supporting LPDDR5X, LPDDR5 and/or LPDDR4X SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems.

Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR5X/5/4X PHY is provided as hardened IP components
(macrocells) to facilitate the following types of signals:
• Single-ended Command/Address (C/A) and Data (DQ) signals
• Differential signals (clock, data strobe, and WCK signals)
• CMOS logic-level based C/A signals

Key Features

Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
Support for data rates up to 8533 Mbps
Designed for rapid integration with Synopsys LPDDR5X/5/4X controller for a complete DDR interface solution
DFI 5.0 controller interface
PHY independent, firmware-based training using an embedded calibration processor
Optional dual channel architecture which facilitates two independent channels in less area versus two independent PHYs
Support for DFI-based low power modes and lower power sleep and retention modes
Support for up to 4 trained states/frequencies
Flexible implementation to support Package-On-Package (PoP) or discrete DRAM-on-PCB systems with optimized PHY architecture
Built-in anti-aging features to prevent effects of NBTI & HCI

Applications

Smartphones and tablets
Embedded mobile computing
Ultraportable laptops / “Ultrabooks”
Automotive
Mobile multimedia
Digital home and office
Wireless connectivity

Deliverables

Executable .run installation file which includes GDSII, LEF files, LVS netlists, .lib/.db timing models, Verilog model, DRC/LVS log
files, I/O IBIS Model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files, sample Verification Environment, PHY
data book, physical implementation guide, app notes, verification guide, installation guide, and implementation checklist
PUB includes Verilog code, Synthesis/ STA constraints and scripts, sample verification environment, and data book
Implementation Guide, Application notes, and quick start manuals
Firmware for training, ATE test and diagnostics
DDR PHY compiler

Technical Specifications

Foundry, Node

Samsung SF5A

Maturity

Available on request

Availability

Available

Samsung

Pre-Silicon: 5nm

TSMC