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ARM Cortex-M3 IP

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  • 32-bit RISC Processor To Deliver High Performance In Low-Cost Microcontroller Applications
    • Powerful debug and non-intrusive real-time trace - Comprehensive debug and trace features dramatically improve developer productivity. It is extremely efficient to develop embedded software with proper debug.
    • Memory Protection Unit (MPU) - Software reliability improves when each module is allowed access only to specific areas of memory required for it to operate. This protection prevents unexpected access that may overwrite critical data.
    • Integrated nested vectored interrupt controller (NVIC) - There is no need for a standalone external interrupt controller. Interrupt handling is taken care of by the NVIC removing the complexity of managing interrupts manually via the processor.
    • Thumb-2 code density - On average, the mix between 16bit and 32bit instructions yields a better code density when compared to 8bit and 16bit architectures. This has significant advantages in terms of reduced memory requirements and maximizing the usage of precious on-chip Flash memory.
    Block Diagram -- 32-bit RISC Processor To Deliver High Performance In Low-Cost Microcontroller Applications
  • Secure AHB Performance Subsystem - ARM M3
    • Quick development start up
    • Low power plus performance to handle most IoT software
    • Integration and software support available
    Block Diagram -- Secure AHB Performance Subsystem - ARM M3
  • Block Diagram -- SecurCore_SC300
  • Small, Low Power, Energy Efficient 32-bit Microcontroller Processor
    • Exceptional code density - on average, the mix between 16-bit and 32-bit instructions yields a better code density when compared to 8-bit and 16-bit architectures. This has significant advantages in terms of reduced memory requirements and maximizing the usage of precious on-chip Flash memory.
    • Binary upward compatible with all other Cortex-M processors - the Cortex-M0 has mainly 16-bit Thumb-2 instructions and few 32-bit ones. These instructions are also present on all the other Cortex-M processors. Hence all code written for the Cortex-M0 will run as is on the other processors.
    • Built-in low-power features - sleep, deep sleep and state retention are three low power modes available to the user
    • Optional Debug Access Port and Serial Wire Debug - for devices where every pin counts the serial wire debug port uses only two pins
    Block Diagram -- Small, Low Power, Energy Efficient 32-bit Microcontroller Processor
  • Tamper-resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M
    • Tamper-resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M
    Block Diagram -- Tamper-resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M
  • Arm Cortex-M33
    • TrustZone for Armv8-M - A foundation for security for embedded devices. TrustZone offers software isolation to code, memory and I/O while retaining the requirements of embedded applications: real-time deterministic response, minimal switching overhead, and ease of software development.
    • Co-processor interface - A dedicated bus for extending the operation of the processor with tightly coupled co-processors to handle frequent and compute intensive operations in an ecosystem friendly manner. The interface supports up to eight accelerators and takes into account the security state of the co-processor.
    • SIMD, saturating arithmetic, fast MAC - Powerful instruction set for accelerating DSP applications, built right into the processor. A highly optimized DSP library built using these instructions is available free-of-charge from the Arm website (CMSIS Library).
    • Memory Protection Unit (MPU) - Software reliability and system security improves when each module is allowed access only to specific areas of memory required for it to operate. This protection prevents unexpected access that may overwrite critical data. Each of the security zones can have a dedicated MPU that may be configured with a different number of regions.
    Block Diagram -- Arm Cortex-M33
  • Telematics Processors IP
    • Core and infrastructure
    • ? ARM® Cortex™-R4 MCU
    • ? Embedded SRAM
    • ? SDRAM controller
  • AMBA APB 3.0 Bus Interface
    • Implements an APB v3.0 bus fabric
    • Supports up to 16 APB slave devices
    • Auto-stitched to slave devices using SmartDesign IP design tool in Libero IDE
    • Fully compatible with Cortex-M3, Cortex-M1, Core8051s, CoreABC and other APB3 IP cores
  • AHB Performance Subsystem - ARM M3
    • Supports Cortex-M3/M4 (or equivalent) processor
    • Power Management Unit
    • AMBA® 2.0 (AHB)
    Block Diagram -- AHB Performance Subsystem - ARM M3
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