Adc for automotive radar IP

The IP consists of a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique.
The ADC IP is configurable regarding resolution (6-13 bit) and sample rate (up to 10kS/s) and power consumption down to 1.9 µW. The input voltage range is quasi-rail-to-rail guaranteeing more than + 1.7 V@ 1.8V power supply.
An optional calibration technique can be applied to compensate degraded mismatch behavior of technology capacitors.

The ADC IP is a general-purpose sigma-delta converter and it is configurable for conversion speed and power consumption with adaptable oversampling ratio.
It is built using typical second order architecture using correlated-double-sampling method. The target application is sampling of transient input voltages with 8k S/s with low-power and 192 kS/s respectively.

64 parallel GNSS signal tracking channels with accurate and precise measurements
Massive and wide bandwidth correlators enable fast acquisition and high precision
Supports all signals in L1, L2, L5 and S band frequencies from GPS, GALILEO, GLONASS, BeiDou, QZSS, IRNSS, and SBAS constellations
Efficient and generic PRN code handling architecture to support future signal structures

ADC for Automotive RADAR IP