64-bit RISC-V CPU IP

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Compare 31 IP from 8 vendors (1 - 10)
  • Ultra-low power consumption out-of-order commercial-grade 64-bit RISC-V CPU IP
    • Dubhe-70 is a 9+ stage, 3-issue, out-of-order CPU IP that supports the rich RISC-V instruction set, RV64GCBH_Zicond_Zicbom_Zicboz_Zicbop.
    • With a score of 7.2 SPECInt2006/GHz, Dubhe-70 targets applications that require highly energy-efficient computation, including mobile, desktop, AI, and automotive.
    Block Diagram -- Ultra-low power consumption out-of-order commercial-grade 64-bit RISC-V CPU IP
  • 64-bit RISC-V CPU with M, Zicsr extensions and External Debug support
    • Five-stage pipeline
    • Harvard architecture
    • RV64I Base RISC-V ISA
    Block Diagram -- 64-bit RISC-V CPU with M, Zicsr extensions and External Debug support
  • 64-bit CPU with RISC-V Vector Extension
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • RISC-V vector extension
    • Vector Processing Unit (VPU) boost the performance of AI, AR/VR, computer vision, cryptography, and multimedia processing
    • Andes extensions, architected for performance and functionality enhancements
    Block Diagram -- 64-bit CPU with RISC-V Vector Extension
  • High Performance 64-bit RISC-V Processor
    • Dubhe-90 is a high-performance commercial RISC-V CPU Core IP that is deliverable.
    • It adopts an 11+ stage and 5-issue pipeline, superscalar, and deep out-of-order execution, and supports standard RISC-V RV64GCBH extensions.
    Block Diagram -- High Performance 64-bit RISC-V Processor
  • 64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
    • 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
    • Symmetric multiprocessing up to 8 cores
    Block Diagram -- 64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
  • RISC-V CPU IP With ISO 26262 Automotive Functional Safety Compliant
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • Floating point extensions
    • Bit-manipulation extensions
    Block Diagram -- RISC-V CPU IP With ISO 26262 Automotive Functional Safety Compliant
  • 64-bit CPU Core with Level-2 Cache Controller
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • Floating point extensions
    • DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
    • Andes extensions, architected for performance and functionality enhancements
    • Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
    Block Diagram -- 64-bit CPU Core with Level-2 Cache Controller
  • 64-bit CPU with Modern RISC Architecture, MemBoost and PMA
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • Floating point extensions
    • DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
    • Andes extensions, architected for performance and functionality enhancements
    • Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
    • 64-bit CPU architecture, enabling software to utilize the memory spaces far beyond 4G bytes imposed by 32-bit CPUs
    Block Diagram -- 64-bit CPU with Modern RISC Architecture, MemBoost and PMA
  • Compact High-Speed 64-bit CPU Core
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • Floating point extension
    • Andes extensions, architected for performance and functionality enhancements
    • Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
    Block Diagram -- Compact High-Speed 64-bit CPU Core
  • Compact High-Speed 64-bit CPU for Real-time and Linux Applications
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • DSP/SIMD ISA to boost the performance of digital signal processing
    • Floating point extension
    • Bit-manipulation extensions
    Block Diagram -- Compact High-Speed 64-bit CPU for Real-time and Linux Applications
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