64-bit RISC-V IP
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64-bit RISC-V high-performance embedded core
- 64-bit RISC-V high-performance embedded core. Ideal for control/compute/acceleration workloads requiring high performance and 64-bit capabilities.
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64-bit RISC-V embedded core with in-order single issue pipeline
- 64-bit RISC-V embedded core with in-order single issue pipeline.
- Optimized for low power and small area.
- Perfectly fits for embedded control.
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64-bit RISC-V core with in-order dual issue pipeline based complex for Linux-based systems
- 64-bit RISC-V core with in-order dual issue pipeline based complex.
- Balanced power efficiency and performance.
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64-bit RISC-V CPU with M, Zicsr extensions and External Debug support
- Five-stage pipeline
- Harvard architecture
- RV64I Base RISC-V ISA
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64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
- 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
- Symmetric multiprocessing up to 8 cores
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64-bit RISC-V Single Core Microprocessor
- RISC-V 64G (RV64IMAFD) ISA
- 6 stage in-order pipeline implementation
- Advanced branch predictor: BTB, BHT, RAS
- Harvard architecture
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64-Bit RISC-V High Performance Processor
- RISC-V RV64 I/M/A/C/F/D/P ISA supported
- ECLIC(Enhanced Core Level Interrupt Controller)
- 6-Stage Pipeline
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64-bit RISC-V Application Processor Core
- High computational throughput with 7-stage pipeline and branch predictor
- Support for RISC-V single and double precision FPU
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64-bit RISC-V Application Processor Core
- 64-bit RISC-V core
- Linux capable
- In-order 7-stage pipeline
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The S5 Series offers 64-bit RISC-V performance with 32-bit power and area
- Up to 8 coherent S5 Cores and optional L2 Cache Controller
- Configurable core performance
- Double precision Floating Point Unit
- Level 1 Memory System and ECC