64-bit RISC-V embedded core with in-order single issue pipeline

Overview

Key Features

• Configurable instruction set architecture:
  • 64-bit RISC-V with 32 integer registers (I extension)
  • Integer multiplication and division (M extension)
  • Atomic operation support (A extension)
  • Compressed mode for better code density (C extension)
  • IEEE 754-2008 compliant single precision floating point (F extension)
  • IEEE 754-2008 compliant double precision floating point (D extension)
  • User mode interrupt handlers (N extension)
  • Bit manipulation instructions support (B extension)
  • Scalar cryptography instructions support (K extension)
  • Digital signal processing instructions support (P extension)
• Single instruction issue
• Machine and User modes
• 8 stage in-order pipeline
• Advanced branch predictor: BTB, BHT, RAS
• Configurable memory subsystem: L1 I/D-caches, TCMs
• Front-port to access TCMs by external masters
• Configurable interrupt subsystem
  • Platform Level Interrupt Controller (PLIC)
  • Core Local Interruptor (CLINT): timer + software interrupts
  • Local interrupt support to provide fast handling
  • Core Local Interrupt Controller (CLIC)
  • Non-Maskable Interrupts (NMIs)
• ECC memory protection (SEC-DED)
• Physical memory protection
• Integrated debug controller including HW breakpoints
• System bus access
• Compact JTAG support
• Trace support
• Power management support
• AXI/AHB configurable interfaces
• Performance
  • 1.81 DMIPS/MHz
  • 3.29 CoreMark/MHz
• Frequency
  • 1.2 GHz (TSMC, 28nm HPC+, SSG corner)

Block Diagram

Technical Specifications