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5nm multi-gigabit copper Ethernet PHY IP

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Compare 148 IP from 15 vendors (1 - 10)
  • 32G PHY in Samsung (10nm, 8nm, 4nm, 5nm, SF2)
    • Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions)
    • Supports back channel initialization, aggregation, bifurcation, and power management
    • Supports both internal and external reference clock connections to the PHY
    • Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces
  • 112G-ULR PAM4 SerDes PHY
    • Supports full-duplex 1.25Gbps to 112.5Gbps data rates
    • Superior bit error rate (BER) performance across high-loss and reflective channels
    • Compliant with IEEE 802.3ck and OIF standard electrical specifications
    • Supports flexible SoC floorplan and IP placement and provides package substrate guideline/reference designs
  • PCIe 5.0/6.0 PHY IP - 5nm, 4nm, 2nm
    • The PCIe 5.0/6.0 PHY IP consists of hardmacro PMA and PCS compliant with PCIe Base 5.0/6.0 specification.
    • This IP offers a cost-effective and low-power solution using FinFET CMOS technology.
    • It includes all ESD I/Os and bump pads and supports extensive built-in self test features such as loopback and scan.
    Block Diagram -- PCIe 5.0/6.0 PHY IP - 5nm, 4nm, 2nm
  • 112G-ELR PAM4 SerDes PHY - TSMC 5nm
    • TSMC 5nm FinFET CMOS Process
    • Power-optimized for ELR and LR links
    • Integrated BIST capable of producing and checking PRBS
    • 56-112Gbps PAM4 or 1-56Gbps NRZ data rates
  • TSMC CLN5PLVT 5nm LPDDR5 PHY - 6400Mbps
    • Supports LPDDR5
    • DFI 5.1 compliant
    • Supports x4, x8 and x16 DRAMs
    • Up to 72 bits wide and up to 4 ranks
    Block Diagram -- TSMC CLN5PLVT 5nm LPDDR5 PHY - 6400Mbps
  • TSMC CLN5PLVT 5nm LPDDR4 PHY - 4266Mbps
    • Supports LPDDR4
    • DFI 5.1 compliant
    • Supports x4, x8 and x16 DRAMs
    • Up to 72 bits wide and up to 4 ranks
    Block Diagram -- TSMC CLN5PLVT 5nm LPDDR4 PHY - 4266Mbps
  • TSMC CLN5PLVT 5nm LPDDR3 PHY - 2133Mbps
    • Supports LPDDR3
    • DFI 5.1 compliant
    • Supports x4, x8 and x16 DRAMs
    • Up to 72 bits wide and up to 4 ranks
    Block Diagram -- TSMC CLN5PLVT 5nm LPDDR3 PHY - 2133Mbps
  • TSMC CLN5P 5nm LPDDR5 PHY - 6400Mbps
    • Supports LPDDR5
    • DFI 5.1 compliant
    • Supports x4, x8 and x16 DRAMs
    • Up to 72 bits wide and up to 4 ranks
    Block Diagram -- TSMC CLN5P 5nm LPDDR5 PHY - 6400Mbps
  • TSMC CLN5P 5nm LPDDR4 PHY - 4266Mbps
    • Supports LPDDR4
    • DFI 5.1 compliant
    • Supports x4, x8 and x16 DRAMs
    • Up to 72 bits wide and up to 4 ranks
    Block Diagram -- TSMC CLN5P 5nm LPDDR4 PHY - 4266Mbps
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