4K2K IP
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16
IP
from 7 vendors
(1
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10)
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HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in ST 28FDSOI
- HDMI version 2.0b compliant transmitter
- Supports CEA-861F/VESA DMT up to 4K2K resolution@60fps
- Supports 3D formats (Frame packing/Side by Side Half/Top & Bottom)
- Wide range channel speed up to 6.0Gbps
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HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
- HDMI version 2.0b compliant transmitter
- Supports CEA-861F/VESA DMT up to 4K2K resolution@60fps
- Supports 3D formats (Frame packing/Side by Side Half/Top & Bottom)
- Wide range channel speed up to 6.0Gbps
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HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
- HDMI version 2.0b compliant transmitter
- Supports CEA-861F/VESA DMT up to 4K2K resolution@60fps
- Supports 3D formats (Frame packing/Side by Side Half/Top & Bottom)
- Wide range channel speed up to 6.0Gbps
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HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in UMC 28HPC
- HDMI version 2.0b compliant transmitter
- Supports CEA-861F/VESA DMT up to 4K2K resolution@60fps
- Supports 3D formats (Frame packing/Side by Side Half/Top & Bottom)
- Wide range channel speed up to 6.0Gbps
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HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP
- HDMI version 2.0b compliant transmitter
- Supports CEA-861F/VESA DMT up to 4K2K resolution@60fps
- Supports 3D formats (Frame packing/Side by Side Half/Top & Bottom)
- Wide range channel speed up to 6.0Gbps
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HDMI 2.0 Receiver with MHL 2.0
- HDMI 2.0 Specification, MHL 2.0 Specification and HDCP 1.4 Specification compliant
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Video Scaler with 4K Up/Down/Cross Conversion (Interleaved/Quadrant)
- Any input <= 4096x2160p scaled to any output <= 4096x2160p
- Supports 2-Sample Interleave and Square Division formats for use with Quad 3G-SDI links
- High quality polyphase scaling
- Invisible seams between tiles
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JPEG Decoder 1-pixel/clock
- - Image Format: Frame sequential method
- - Input/Output Format: YUV 4:4:4/4:2:2/4:2:0/4:0:0
- - Data bus protcol: AXI
- - CPU bus protcol: AHB
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JPEG Encoder 1-pixel/clock
- - Image Format: Frame sequential method
- - Input/Output Format: YUV 4:4:4/4:2:2/4:2:0/4:0:0
- - Data bus protcol: AXI
- - CPU bus protcol: AHB
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HDMI 2.0 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP
- HDMI version 2.0b compliant receive.
- Supports HDCP 2.2/HDCP 1.4.
- Supports CEA-861F/VESA DMT up to 4K2K.
- Supports 3D formats (Frame packing/Side by Side Half/Top & Bottom).