HDMI 2.0 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP

Overview

The HDMI 2.O Rx IP complies with version 2.0b of the HDMI specification and offers the full functionality of an HDMI receiver. Physical layer (PHY) and link module make up its two modules. The PHY is upper compatible with DVI receiver and implemented as a hard IP based on TSMC 28HPC+ CMOS logic process, while the link module is implemented as a synthesizable soft IP. The transmission of audio visual content is shielded using an HDCP (High-bandwidth Digital Content Protection) encryption that is built-in.

Key Features

HDMI version 2.0b compliant receive.
Supports HDCP 2.2/HDCP 1.4.
Supports CEA-861F/VESA DMT up to 4K2K.
Supports 3D formats (Frame packing/Side by Side Half/Top & Bottom).
Wide range channel speed up to 6.0Gbps.
Deep Color Mode support at 24, 30, and 36 bit per pixel.
Programmable color space converter includes BT601/709/2020(NonConst)/RGB/xvYCC.
Adjustable analog characteristics.
Supports I2S, S/PDIF and DSD audios.
1.8V/0.9V power supply.
Full testability.
3D formats with Frame Packing/Side by Side Half/Top & Bottom.
Silicon Proven in TSMC 40LP

Applications

Digital TV
Tablets
Mobile phones
Digital camera
Camcorders
Soundbars
Audio/Video Receivers
DVD players
Recorders
Streaming-media players
Set-top boxes
Home theater systems
Game consoles

Deliverables

RTL code
GDS2 at foundry merge
Documentations included Link and PHY specifications
SoC integration guidelines
Board level design guidelines to pass HDMI certification

Technical Specifications

Foundry, Node

TSMC 40LP

Maturity

In Production

Availability

Immediate

TSMC

In Production: 40nm LP

UMC