3D I/O IP

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TSMC (6)

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3nm (3)
5nm (3)

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Silicon IP (12)

Compare 12 IP from 7 vendors (1 - 10)

3D Resistive RAM - High-Density Memory
OpenGL® ES2.0 compatible 3D graphics IP core
- The smallest class 3D graphics IP core, 0.48mm² in silicon footprint
- Full OpenGL ES 2.0 capability
- Ultra-low power consumption
NVMe SSD Controller Platform
- The PCIe-NVMe SSD controller platform is compliant with NVM Express 1.2 specification and targets for both enterprise and client SSD markets.
- It features YEESTOR's NVMe controller core and LDPC error correction core to enable low-power and cost-effective SSD controllers that support 1x/1y/1z MLC/TLC and 3D NAND.
TSMC N3P Source Sync 3DIO PHY
- Optimized for heterogeneous integration in 3D stacking
- Enabling designers the flexibility and scalability to accelerate multi-die integration
- Optimal PPA architected to supporting 2.5D and 3D packages
- Versatile offering tuned for optimal use scenarios, including:
TSMC N3P Source Sync 3DIO Library
- Optimized for heterogeneous integration in 3D stacking
- Enabling designers the flexibility and scalability to accelerate multi-die integration
- Optimal PPA architected to supporting 2.5D and 3D packages
- Versatile offering tuned for optimal use scenarios, including:
TSMC N3P 3DIO Library
- Optimized for heterogeneous integration in 3D stacking
- Enabling designers the flexibility and scalability to accelerate multi-die integration
- Optimal PPA architected to supporting 2.5D and 3D packages
- Versatile offering tuned for optimal use scenarios, including:
TSMC N5 Source Sync 3DIO Library
- Optimized for heterogeneous integration in 3D stacking
- Enabling designers the flexibility and scalability to accelerate multi-die integration
- Optimal PPA architected to supporting 2.5D and 3D packages
- Versatile offering tuned for optimal use scenarios, including:
Synopsys Synthesizable 3DIO IP for Flexible Physical Implementation
- Optimized for heterogeneous integration in 3D stacking
- Enabling designers the flexibility and scalability to accelerate multi-die integration
- Optimal PPA architected to supporting 2.5D and 3D packages
- Versatile offering tuned for optimal use scenarios, including:
3DIO PHY IP for TSMC N5
- Optimized for heterogeneous integration in 3D stacking
- TSMC N5
Quad channel ADAS IP platform
- Can cut design cost and time to market by up to 30%.