PCIe-NVMe SSD Controller Platform
Overview
YEESTOR’ PCIe-NVMe SSD controller platform (Libra) is compliant with NVM Express specification and targets for both enterprise and client SSD markets. It features YEESTOR’s Meissa NVMe controller core and Alcyone LDPC error correction core to enable low-power and cost-effective SSD controllers that support 1x/1y/1z MLC/TLC and 3D NAND. Libra SSD architecture delivers industry-leading IOPS and latency performance. With YEESTOR’s performance management, Libra is able to achieve consistent performance for different workloads and this is especially important for data center applications. The endurance management of Libra along with YEESTOR’s dynamic VCR LDPC and advanced FTL combined as the ExtEnd™ technology that can either extend product life cycle or expand capacity (hence reduce the BOM cost) of SSD. Libra has been implemented on the FPGA platform and allows customers to develop FW in parallel with ASIC development.
Key Features
- Compliant to NVMe specification (pass UNH-IOL compliance test)
- PCIe Gen3 (2/4/8-lanes based on customers’ requirements)
- Meissa NVMe Controller Core
- Alcyone LDPC Error Correction Core
- Data Reduction Engine
- Reduce write amplification
- Increase usable over provisioning
- Security Engine
- TCG-Opal
- NAND flash Interface
- Support ONFI 3.0 SDR mode 0 and NV-DDR2 Mode 0~7 (400 MT/s)
- Support Toggle 2, Up to 400MT/s
- Support SLC/MLC/TLC 3D NAND flash
- Fully programmable timing generator
- Up to 16 Channels, 16 die per channel
- Support hardware IO throttling
- FTL FW, can be ported to different CPUs based on customers’ requirement
- Advanced Data Manager
- Centralized data buffer and queue management
- Performance management
- Ensure consistent performance for different workload
Benefits
- Reducing Time-to-Market
- Firmware and ASIC development
- Pass UNH-IOL compliance test
Block Diagram
Applications
- PCIe-NVMe Client SSD Controller
- PCIe-NVMe Enterprise SSD Controller
- PCIe-NVMe Data Center SSD Controller
Deliverables
- RTL code for both ASIC and FPGA
- Verilog direct test verification environment
- Synthesis script for Synopsys Design Compiler and Xilinx FPGA
- Reference firmware
- Documentation
- Datasheet
- Integration guide
- Programming guide
- Register specifications
Technical Specifications
Maturity
Silicon Proven
Availability
available, Customization/Design Service is also available