32-bit CPU IP
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196
IP
from 40 vendors
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10)
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Scalable & Royalty-Free 32-bit CPU
- Configurable 32-bit Harvard architecture
- Performance up to 1.48 / 2.67 DMIPS/MHz and 2.41 CoreMarks/MHz
- Small footprint starting at 10.6k/6.8k ASIC gates
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Compact High-Speed 32-bit CPU Core with Level-2 Cache
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
- Andes extensions, architected for performance and functionality enhancements
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Compact High-Speed 32-bit CPU Core with MemBoost and PMA
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
- Andes extensions, architected for performance and functionality enhancements
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Compact High-Speed 32-bit CPU Core with DSP
- AndeStar™ V5 ISA, compliant to RISC-V technology
- DSP/SIMD ISA to boost the performance of digital signal processing
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Compact High-Speed 32-bit CPU Core
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- Andes extensions, architected for performance and functionality enhancements
- Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
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Compact High-Speed 32-bit CPU for Real-time and Linux Applications
- AndeStar V5 ISA, compliant to RISC-V
- Floating point extensions
- Andes extensions
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32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications
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High-performance 32-bit RISC CPU
- 32-bit RISC architecture
- 16 or 32 general purpose registers
- 104 basic instructions and 10 addressing modes
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Compact, low-power 32-bit RISC CPU
- 32-bit RISC architecture
- 16 or 32 general purpose registers
- 104 basic instructions and 10 addressing modes
- Optional IEEE 754 floating point unit (FPU)
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H8SX CPU subsystem (H8SX C3000) IP
- An original subsystem for SoCs other than microcontrollers
- 3 type interfaces available to connect user functions or IPs
- 3 type data transfer functions
- 3 type timers
