IP Catalog > 224G PHY

224G PHY IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (15)
Compare 15 IP from 3 vendors (1 - 10)
  • 224G Ethernet PHY, TSMC N3P x1, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 224Gbps data rates
    • Enables 200G, 400G, 800G, and 1.6T Ethernet
    • Ethernet interconnects for wired network infrastructure
    • Supports IEEE 802.3 and OIF-224G standards electrical specifications
    Block Diagram -- 224G Ethernet PHY, TSMC N3P x1, North/South (vertical) poly orientation
  • 224G Ethernet PHY, TSMC N2P x4, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 224Gbps data rates
    • Enables 200G, 400G, 800G, and 1.6T Ethernet
    • Ethernet interconnects for wired network infrastructure
    • Supports IEEE 802.3 and OIF-224G standards electrical specifications
    Block Diagram -- 224G Ethernet PHY, TSMC N2P x4, North/South (vertical) poly orientation
  • 224G Ethernet PHY, Intel 18A x4, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 224Gbps data rates
    • Enables 200G, 400G, 800G, and 1.6T Ethernet
    • Ethernet interconnects for wired network infrastructure
    • Supports IEEE 802.3 and OIF-224G standards electrical specifications
    Block Diagram -- 224G Ethernet PHY, Intel 18A x4, North/South (vertical) poly orientation
  • 224G Ethernet PHY in TSMC (N3E)
    • Optimized for performance, power, and area
    • Includes one, two, or four full-duplex PAM-4/6 transceivers (transmit and receive functions)
    • Supports IEEE and OIF-CEI-224G standards
    • Includes auto-negotiation and link training capabilities
  • 224G Ethernet PHY for TSMC 3nm
    • Supports full-duplex 1.25 to 224Gbps data rates
    • Enables 200G, 400G, 800G, and 1.6T Ethernet
    • Ethernet interconnects for wired network infrastructure
  • 224G Ethernet PHY, TSMC N3E x4, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 224Gbps data rates
    • Enables 200G, 400G, 800G, and 1.6T Ethernet
    • Ethernet interconnects for wired network infrastructure
    • Supports IEEE 802.3 and OIF-224G standards electrical specifications
    Block Diagram -- 224G Ethernet PHY, TSMC N3E x4, North/South (vertical) poly orientation
  • 224G SerDes PHY and controller for UALink for AI systems
    • UALink, the standard for AI accelerator interconnects, facilitates this scalability by providing low-latency, high-bandwidth communication.
    • As a member of the UALink Consortium, Cadence offers verified UALink IP subsystems, including controllers and silicon-proven PHYs, optimized for robust performance in both short and long-reach applications and delivering industry-leading power, performance, and area (PPA).
    Block Diagram -- 224G SerDes PHY and controller for UALink for AI systems
  • 224G-LR SerDes PHY enables 1.6T and 800G networks
    • Optimized Performance, Power and Area with Design Agility
    • Supports full-duplex 1.25 to 225Gbps data rates
    • Enables 1.6T, 800G, 400G, and 200G Ethernet with a PHY + Controller solution
    • Supports evolving IEEE 802.3 and OIF-CEI-224G standard electrical specifications
    • Meets the performance requirements of chip-to-module (VSR), chip-to-chip (MR), and copper/backplane (LR) interconnects
    Block Diagram -- 224G-LR SerDes PHY enables 1.6T and 800G networks
  • HPC MACsec Security Modules for Ethernet
    • IEEE 802.1ae, IEEE 802.1br Support
    • 100 Gbps—1.6 Tbps
    • Can reach higher throughputs scalable to 3.2 Tbps
    • Supports also lower performance modes down to 10 Gbps
  • UALinkSec Security Module
    • UALink 200 v1.0 / UALinkSec​ specification support
    • Plug and play with Synopsys UALink controller
    • Supports 200 GT/s per lane​, enabled by silicon-proven Synopsys 224G PHY IP
    • Support bifurcation of up to 4 ports​
×
Semiconductor IP