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16Gbps SerDes IP

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Compare 16 IP from 7 vendors (1 - 10)
  • 16Gbps SerDes IP on TSMC 12nm
    Block Diagram -- 16Gbps SerDes IP on TSMC 12nm
  • Ethernet SerDes - 16Gbps and 10Gbps multi-protocol SerDes PHY
    • Wide range of protocols that support networking, HPC, and applications
    • Low-latency, long-reach, and low-power modes
    • Multi-Link PHY—mix protocols within the same macro
    • EyeSurf —non-destructive on-chip oscilloscope
    • Extensive set of isolation, test modes, and loop-backs including APB and JTAG
    • Supports 16-bit, 20-bit, and 32-bit PIPE and non-PIPE interfaces
    • Selectable serial pin polarity reversal for both transmit and receive paths
    Block Diagram -- Ethernet SerDes - 16Gbps and 10Gbps multi-protocol SerDes PHY
  • 16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
    • Support PCIe G1 to G4 with PCS soft-macro supporting PIPE 4.4.1
    • Support xPON applications: Sym/Asym GPON, Sym/Asym 10GPON, Sym EPON, Sym/Asym 10GEPON
    Block Diagram -- 16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
  • 32Gbps SerDes PHY in GF 22nm
    • This 32Gbps SerDes PHY is implemented in GlobalFoundries 22FDX CMOS technology and provides a high-performance, protocol-agnostic serial interface for advanced mixed-signal and high-speed digital SoCs.
    • The PHY is architected as a modular design consisting of a low-jitter clock multiplier, a half-rate transmitter with digitally programmable feed-forward equalization, and a configurable CTLE-based receiver with digital clock-and-data recovery, supporting both 16 Gbps and 32 Gbps operation.
    Block Diagram -- 32Gbps SerDes PHY in GF 22nm
  • PCIe Express Gen4 / Ethernet SERDES on TSMC CLN5A
    • Industry leading low power PMA macro – 122.9mW per lane at 16Gbps (7.7mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Support for Ethernet protocols and Automotive Grade 2
    • Compact form factor – 0.34 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • PCI Express Gen5 SERDES PHY on Samsung 8LPP
    • Industry leading low power PMA macro – 224mW per lane at 28Gbps (8.0 mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.38 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    • Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
  • PCI Express Gen4 SERDES PHY on Samsung 7LPP
    • Industry leading low power PMA macro – 132.7mW per lane at 16Gbps (8.4mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.32 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    • Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
  • PCI Express Gen4 / Ethernet SERDES on TSMC CLN5
    • Industry leading low power PMA macro – 122.9mW per lane at 16Gbps (7.7mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Support for Ethernet protocols and Automotive Grade 2
    • Compact form factor – 0.34 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • PCI Express Gen3/4 Enterprise Class SERDES PHY on Samsung 14LPP
    • Industry leading low power PMA macro – 132.7mW per lane at 16Gbps (8.4mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.266 mm2 active silicon area per lane including ESD
    • Enterprise class Long Reach 5-tap DFE supporting beyond standard PCIe Channels
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • PCI Express Gen3 SERDES PHY on Samsung 7LPP
    • Industry leading low power PMA macro – 36mW per lane at 8Gbps (4.5mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.1 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    • Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
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